Lines Matching refs:ui32ConfigValue

67     uint32_t ui32ConfigValue;  in am_hal_wdt_config()  local
76 ui32ConfigValue = 0; in am_hal_wdt_config()
81 ui32ConfigValue |= _VAL2FLD(WDT_CFG_CLKSEL, psConfig->eClockSource); in am_hal_wdt_config()
82 ui32ConfigValue |= _VAL2FLD(WDT_CFG_INTVAL, psConfig->ui32InterruptValue); in am_hal_wdt_config()
83 ui32ConfigValue |= _VAL2FLD(WDT_CFG_RESVAL, psConfig->ui32ResetValue); in am_hal_wdt_config()
87 ui32ConfigValue |= _VAL2FLD(WDT_CFG_DSPRESETINTEN, 1); in am_hal_wdt_config()
92 ui32ConfigValue |= _VAL2FLD(WDT_CFG_RESEN, 1); in am_hal_wdt_config()
97 ui32ConfigValue |= _VAL2FLD(WDT_CFG_INTEN, 1); in am_hal_wdt_config()
103 WDT->CFG = ui32ConfigValue; in am_hal_wdt_config()
129 uint32_t ui32ConfigValue = 0; in dsp_wdt_config() local
138 ui32ConfigValue |= _FLD2VAL(WDT_DSP0CFG_DSP0PMRESVAL, psConfig->ui32PMResetValue); in dsp_wdt_config()
139 ui32ConfigValue |= _FLD2VAL(WDT_DSP0CFG_DSP0INTVAL, psConfig->ui32InterruptValue); in dsp_wdt_config()
140 ui32ConfigValue |= _FLD2VAL(WDT_DSP0CFG_DSP0RESVAL, psConfig->ui32ResetValue); in dsp_wdt_config()
144 ui32ConfigValue |= _FLD2VAL(WDT_DSP0CFG_DSP0PMRESEN, 1); in dsp_wdt_config()
149 ui32ConfigValue |= _FLD2VAL(WDT_DSP0CFG_DSP0RESEN, 1); in dsp_wdt_config()
154 ui32ConfigValue |= _FLD2VAL(WDT_DSP0CFG_DSP0INTEN, 1); in dsp_wdt_config()
160 WDT->DSP0CFG = ui32ConfigValue; in dsp_wdt_config()
167 ui32ConfigValue |= _FLD2VAL(WDT_DSP1CFG_DSP1PMRESVAL, psConfig->ui32PMResetValue); in dsp_wdt_config()
168 ui32ConfigValue |= _FLD2VAL(WDT_DSP1CFG_DSP1INTVAL, psConfig->ui32InterruptValue); in dsp_wdt_config()
169 ui32ConfigValue |= _FLD2VAL(WDT_DSP1CFG_DSP1RESVAL, psConfig->ui32ResetValue); in dsp_wdt_config()
173 ui32ConfigValue |= _FLD2VAL(WDT_DSP1CFG_DSP1PMRESEN, 1); in dsp_wdt_config()
178 ui32ConfigValue |= _FLD2VAL(WDT_DSP1CFG_DSP1RESEN, 1); in dsp_wdt_config()
183 ui32ConfigValue |= _FLD2VAL(WDT_DSP1CFG_DSP1INTEN, 1); in dsp_wdt_config()
189 WDT->DSP1CFG = ui32ConfigValue; in dsp_wdt_config()