468 	ui32GPCfgAddr = AM_REGADDR(GPIO, CFGA) + ((ui32GpioNum >> 1) & ~0x3);  in am_hal_gpio_pinconfig_get()
469 	ui32PadregAddr = AM_REGADDR(GPIO, PADREGA) + (ui32GpioNum & ~0x3);  in am_hal_gpio_pinconfig_get()
470 	ui32AltpadAddr = AM_REGADDR(GPIO, ALTPADCFGA) + (ui32GpioNum & ~0x3);  in am_hal_gpio_pinconfig_get()
775     ui32GPCfgAddr       = AM_REGADDR(GPIO, CFGA)       + ((ui32Pin >> 1) & ~0x3);  in am_hal_gpio_pinconfig()
776     ui32PadregAddr      = AM_REGADDR(GPIO, PADREGA)    + (ui32Pin & ~0x3);  in am_hal_gpio_pinconfig()
777     ui32AltpadAddr      = AM_REGADDR(GPIO, ALTPADCFGA) + (ui32Pin & ~0x3);  in am_hal_gpio_pinconfig()
801     GPIO->PADKEY = GPIO_PADKEY_PADKEY_Key;  in am_hal_gpio_pinconfig()
807     GPIO->PADKEY = 0;  in am_hal_gpio_pinconfig()
957     ui32Regval    = AM_REGVAL( AM_REGADDR(GPIO, PADREGA) + (ui32Pin & ~0x3) );  in am_hal_gpio_state_read()
981             ui32ReadValue = AM_REGVAL(AM_REGADDR(GPIO, RDA) + ui32BaseAddr);  in am_hal_gpio_state_read()
985             ui32ReadValue = AM_REGVAL(AM_REGADDR(GPIO, WTA) + ui32BaseAddr);  in am_hal_gpio_state_read()
989             ui32ReadValue = AM_REGVAL(AM_REGADDR(GPIO, ENA) + ui32BaseAddr);  in am_hal_gpio_state_read()
1044     ui32Regval    = AM_REGVAL( AM_REGADDR(GPIO, PADREGA) + (ui32Pin & ~0x3) );  in am_hal_gpio_state_write()
1061             AM_REGVAL(AM_REGADDR(GPIO, WTSA) + ui32Off) = ui32Mask;  in am_hal_gpio_state_write()
1064             AM_REGVAL(AM_REGADDR(GPIO, WTCA) + ui32Off) = ui32Mask;  in am_hal_gpio_state_write()
1067             AM_REGVAL(AM_REGADDR(GPIO, WTA) + ui32Off) ^= ui32Mask;  in am_hal_gpio_state_write()
1070             AM_REGVAL(AM_REGADDR(GPIO, ENSA) + ui32Off) = ui32Mask;  in am_hal_gpio_state_write()
1073             AM_REGVAL(AM_REGADDR(GPIO, ENCA) + ui32Off) = ui32Mask;  in am_hal_gpio_state_write()
1076             AM_REGVAL(AM_REGADDR(GPIO, ENCA) + ui32Off) ^= ui32Mask;  in am_hal_gpio_state_write()
1112     GPIO->INT0EN |= pGpioIntMask->U.Msk[0];  in am_hal_gpio_interrupt_enable()
1113     GPIO->INT1EN |= pGpioIntMask->U.Msk[1];  in am_hal_gpio_interrupt_enable()
1114     GPIO->INT2EN |= pGpioIntMask->U.Msk[2];  in am_hal_gpio_interrupt_enable()
1154     GPIO->INT0EN &= ~pGpioIntMask->U.Msk[0];  in am_hal_gpio_interrupt_disable()
1155     GPIO->INT1EN &= ~pGpioIntMask->U.Msk[1];  in am_hal_gpio_interrupt_disable()
1156     GPIO->INT2EN &= ~pGpioIntMask->U.Msk[2];  in am_hal_gpio_interrupt_disable()
1195     GPIO->INT0CLR |= pGpioIntMask->U.Msk[0];  in am_hal_gpio_interrupt_clear()
1196     GPIO->INT1CLR |= pGpioIntMask->U.Msk[1];  in am_hal_gpio_interrupt_clear()
1197     GPIO->INT2CLR |= pGpioIntMask->U.Msk[2];  in am_hal_gpio_interrupt_clear()
1248         ui32Mask[0] = GPIO->INT0EN;  in am_hal_gpio_interrupt_status_get()
1249         ui32Mask[1] = GPIO->INT1EN;  in am_hal_gpio_interrupt_status_get()
1250         ui32Mask[2] = GPIO->INT2EN;  in am_hal_gpio_interrupt_status_get()
1253     pGpioIntMask->U.Msk[0] = GPIO->INT0STAT & ui32Mask[0];  in am_hal_gpio_interrupt_status_get()
1254     pGpioIntMask->U.Msk[1] = GPIO->INT1STAT & ui32Mask[1];  in am_hal_gpio_interrupt_status_get()
1255     pGpioIntMask->U.Msk[2] = GPIO->INT2STAT & ui32Mask[2];  in am_hal_gpio_interrupt_status_get()
1456     ui32Regval    = AM_REGVAL( AM_REGADDR(GPIO, PADREGA) + (ui32Pin & ~0x3) );  in am_hal_gpio_isinput()
1481     ui32Padval   = AM_REGVAL( AM_REGADDR(GPIO, PADREGA) + (ui32Pin & ~0x3) );  in am_hal_gpio_isgpio()
1494     ui32Cfgval = AM_REGVAL( AM_REGADDR(GPIO, CFGA) + ((ui32Pin >> 1) & ~0x3) );  in am_hal_gpio_isgpio()