Lines Matching refs:i2s
32 int MXC_I2S_RevA_Init(mxc_i2s_reva_regs_t *i2s, mxc_i2s_req_t *req);
34 int MXC_I2S_RevA_Shutdown(mxc_i2s_reva_regs_t *i2s);
36 int MXC_I2S_RevA_ConfigData(mxc_i2s_reva_regs_t *i2s, mxc_i2s_req_t *req);
38 void MXC_I2S_RevA_TXEnable(mxc_i2s_reva_regs_t *i2s);
40 void MXC_I2S_RevA_TXDisable(mxc_i2s_reva_regs_t *i2s);
42 void MXC_I2S_RevA_RXEnable(mxc_i2s_reva_regs_t *i2s);
44 void MXC_I2S_RevA_RXDisable(mxc_i2s_reva_regs_t *i2s);
46 int MXC_I2S_RevA_SetRXThreshold(mxc_i2s_reva_regs_t *i2s, uint8_t threshold);
48 int MXC_I2S_RevA_SetFrequency(mxc_i2s_reva_regs_t *i2s, mxc_i2s_ch_mode_t mode, uint16_t clkdiv);
50 int MXC_I2S_RevA_SetSampleRate(mxc_i2s_reva_regs_t *i2s, uint32_t smpl_rate,
53 int MXC_I2S_RevA_GetSampleRate(mxc_i2s_reva_regs_t *i2s, uint32_t src_clk);
55 int MXC_I2S_RevA_CalculateClockDiv(mxc_i2s_reva_regs_t *i2s, uint32_t smpl_rate,
58 void MXC_I2S_RevA_Flush(mxc_i2s_reva_regs_t *i2s);
60 int MXC_I2S_RevA_FillTXFIFO(mxc_i2s_reva_regs_t *i2s, void *txData, mxc_i2s_wsize_t wordSize,
63 int MXC_I2S_RevA_ReadRXFIFO(mxc_i2s_reva_regs_t *i2s, void *rxData, mxc_i2s_wsize_t wordSize,
66 void MXC_I2S_RevA_EnableInt(mxc_i2s_reva_regs_t *i2s, uint32_t flags);
68 void MXC_I2S_RevA_DisableInt(mxc_i2s_reva_regs_t *i2s, uint32_t flags);
70 int MXC_I2S_RevA_GetFlags(mxc_i2s_reva_regs_t *i2s);
72 void MXC_I2S_RevA_ClearFlags(mxc_i2s_reva_regs_t *i2s, uint32_t flags);
74 int MXC_I2S_RevA_Transaction(mxc_i2s_reva_regs_t *i2s, mxc_i2s_req_t *i2s_req);
76 int MXC_I2S_RevA_TransactionAsync(mxc_i2s_reva_regs_t *i2s, mxc_i2s_req_t *i2s_req);
78 int MXC_I2S_RevA_TXDMAConfig(mxc_i2s_reva_regs_t *i2s, void *src_addr, int len);
80 int MXC_I2S_RevA_RXDMAConfig(mxc_i2s_reva_regs_t *i2s, void *dest_addr, int len);
82 void MXC_I2S_RevA_Handler(mxc_i2s_reva_regs_t *i2s);