Lines Matching refs:i2s
58 static void configure_data_sizes(mxc_i2s_reva_regs_t *i2s, uint8_t bits_word, uint8_t smp_sz, in configure_data_sizes() argument
62 MXC_SETFIELD(i2s->ctrl1ch0, MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD, in configure_data_sizes()
65 MXC_SETFIELD(i2s->ctrl1ch0, MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD, in configure_data_sizes()
72 MXC_SETFIELD(i2s->ctrl1ch0, MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE, in configure_data_sizes()
75 MXC_SETFIELD(i2s->ctrl1ch0, MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE, in configure_data_sizes()
80 MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_WSIZE, in configure_data_sizes()
85 int MXC_I2S_RevA_Init(mxc_i2s_reva_regs_t *i2s, mxc_i2s_req_t *req) in MXC_I2S_RevA_Init() argument
98 i2s->ctrl0ch0 |= (req->stereoMode << MXC_F_I2S_REVA_CTRL0CH0_STEREO_POS); in MXC_I2S_RevA_Init()
102 i2s->ctrl0ch0 |= (2 << MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL_POS); in MXC_I2S_RevA_Init()
105 MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_ALIGN, in MXC_I2S_RevA_Init()
117 int MXC_I2S_RevA_Shutdown(mxc_i2s_reva_regs_t *i2s) in MXC_I2S_RevA_Shutdown() argument
128 i2s->ctrl0ch0 = 0x00; in MXC_I2S_RevA_Shutdown()
129 i2s->dmach0 = 0x00; in MXC_I2S_RevA_Shutdown()
130 i2s->ctrl1ch0 = 0x00; in MXC_I2S_RevA_Shutdown()
132 i2s->ctrl0ch0 |= MXC_F_I2S_REVA_CTRL0CH0_RST; //Reset channel in MXC_I2S_RevA_Shutdown()
137 int MXC_I2S_RevA_ConfigData(mxc_i2s_reva_regs_t *i2s, mxc_i2s_req_t *req) in MXC_I2S_RevA_ConfigData() argument
158 i2s->ctrl0ch0 &= ~MXC_F_I2S_REVA_CTRL0CH0_WSIZE; in MXC_I2S_RevA_ConfigData()
159 i2s->ctrl1ch0 &= ~MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD; in MXC_I2S_RevA_ConfigData()
160 i2s->ctrl1ch0 &= ~MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE; in MXC_I2S_RevA_ConfigData()
162 configure_data_sizes(i2s, req->bitsWord, req->sampleSize, req->wordSize); in MXC_I2S_RevA_ConfigData()
164 MXC_SETFIELD(i2s->ctrl1ch0, MXC_F_I2S_REVA_CTRL1CH0_ADJUST, in MXC_I2S_RevA_ConfigData()
212 void MXC_I2S_RevA_TXEnable(mxc_i2s_reva_regs_t *i2s) in MXC_I2S_RevA_TXEnable() argument
214 MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_TX_EN, in MXC_I2S_RevA_TXEnable()
218 void MXC_I2S_RevA_TXDisable(mxc_i2s_reva_regs_t *i2s) in MXC_I2S_RevA_TXDisable() argument
220 MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_TX_EN, in MXC_I2S_RevA_TXDisable()
224 void MXC_I2S_RevA_RXEnable(mxc_i2s_reva_regs_t *i2s) in MXC_I2S_RevA_RXEnable() argument
226 MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_RX_EN, in MXC_I2S_RevA_RXEnable()
230 void MXC_I2S_RevA_RXDisable(mxc_i2s_reva_regs_t *i2s) in MXC_I2S_RevA_RXDisable() argument
232 MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_RX_EN, in MXC_I2S_RevA_RXDisable()
236 int MXC_I2S_RevA_SetRXThreshold(mxc_i2s_reva_regs_t *i2s, uint8_t threshold) in MXC_I2S_RevA_SetRXThreshold() argument
242 i2s->ctrl0ch0 |= (threshold << MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL_POS); in MXC_I2S_RevA_SetRXThreshold()
247 int MXC_I2S_RevA_SetFrequency(mxc_i2s_reva_regs_t *i2s, mxc_i2s_ch_mode_t mode, uint16_t clkdiv) in MXC_I2S_RevA_SetFrequency() argument
249 i2s->ctrl1ch0 &= ~MXC_F_I2S_REVA_CTRL1CH0_EN; in MXC_I2S_RevA_SetFrequency()
251 MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_CH_MODE, in MXC_I2S_RevA_SetFrequency()
254 i2s->ctrl1ch0 |= ((uint32_t)clkdiv) << MXC_F_I2S_REVA_CTRL1CH0_CLKDIV_POS; in MXC_I2S_RevA_SetFrequency()
256 i2s->ctrl1ch0 |= MXC_F_I2S_REVA_CTRL1CH0_EN; in MXC_I2S_RevA_SetFrequency()
261 int MXC_I2S_RevA_SetSampleRate(mxc_i2s_reva_regs_t *i2s, uint32_t smpl_rate, in MXC_I2S_RevA_SetSampleRate() argument
266 clk_div = MXC_I2S_RevA_CalculateClockDiv(i2s, smpl_rate, smpl_sz, src_clk); in MXC_I2S_RevA_SetSampleRate()
271 i2s->ctrl1ch0 &= ~MXC_F_I2S_REVA_CTRL1CH0_EN; in MXC_I2S_RevA_SetSampleRate()
272 i2s->ctrl1ch0 |= ((uint32_t)clk_div) << MXC_F_I2S_REVA_CTRL1CH0_CLKDIV_POS; in MXC_I2S_RevA_SetSampleRate()
273 i2s->ctrl1ch0 |= MXC_F_I2S_REVA_CTRL1CH0_EN; in MXC_I2S_RevA_SetSampleRate()
275 return MXC_I2S_RevA_GetSampleRate(i2s, src_clk); in MXC_I2S_RevA_SetSampleRate()
278 int MXC_I2S_RevA_GetSampleRate(mxc_i2s_reva_regs_t *i2s, uint32_t src_clk) in MXC_I2S_RevA_GetSampleRate() argument
283 word_sz = (i2s->ctrl0ch0 & MXC_F_I2S_REVA_CTRL0CH0_WSIZE) >> MXC_F_I2S_REVA_CTRL0CH0_WSIZE_POS; in MXC_I2S_RevA_GetSampleRate()
284 clk_div = (i2s->ctrl1ch0 & MXC_F_I2S_REVA_CTRL1CH0_CLKDIV) >> in MXC_I2S_RevA_GetSampleRate()
306 int MXC_I2S_RevA_CalculateClockDiv(mxc_i2s_reva_regs_t *i2s, uint32_t smpl_rate, in MXC_I2S_RevA_CalculateClockDiv() argument
335 void MXC_I2S_RevA_Flush(mxc_i2s_reva_regs_t *i2s) in MXC_I2S_RevA_Flush() argument
337 i2s->ctrl0ch0 |= MXC_F_I2S_REVA_CTRL0CH0_FLUSH; in MXC_I2S_RevA_Flush()
339 while (i2s->ctrl0ch0 & MXC_F_I2S_REVA_CTRL0CH0_FLUSH) {} in MXC_I2S_RevA_Flush()
364 int MXC_I2S_RevA_FillTXFIFO(mxc_i2s_reva_regs_t *i2s, void *txData, mxc_i2s_wsize_t wordSize, in MXC_I2S_RevA_FillTXFIFO() argument
381 8 - ((i2s->dmach0 & MXC_F_I2S_REVA_DMACH0_TX_LVL) >> MXC_F_I2S_REVA_DMACH0_TX_LVL_POS); in MXC_I2S_RevA_FillTXFIFO()
387 i2s->fifoch0 = fifo_write; in MXC_I2S_RevA_FillTXFIFO()
393 static void read_rx_fifo(mxc_i2s_reva_regs_t *i2s, void *rxData, mxc_i2s_wsize_t wordSize, int cnt) in read_rx_fifo() argument
395 uint32_t fifo_val = i2s->fifoch0; in read_rx_fifo()
415 int MXC_I2S_RevA_ReadRXFIFO(mxc_i2s_reva_regs_t *i2s, void *rxData, mxc_i2s_wsize_t wordSize, in MXC_I2S_RevA_ReadRXFIFO() argument
431 fifo_avail = (i2s->dmach0 & MXC_F_I2S_REVA_DMACH0_RX_LVL) >> MXC_F_I2S_REVA_DMACH0_RX_LVL_POS; in MXC_I2S_RevA_ReadRXFIFO()
433 read_rx_fifo(i2s, rxData, wordSize, received + smpl_cnt); in MXC_I2S_RevA_ReadRXFIFO()
435 fifo_avail = (i2s->dmach0 & MXC_F_I2S_REVA_DMACH0_RX_LVL) >> in MXC_I2S_RevA_ReadRXFIFO()
442 void MXC_I2S_RevA_EnableInt(mxc_i2s_reva_regs_t *i2s, uint32_t flags) in MXC_I2S_RevA_EnableInt() argument
444 i2s->inten |= flags; in MXC_I2S_RevA_EnableInt()
447 void MXC_I2S_RevA_DisableInt(mxc_i2s_reva_regs_t *i2s, uint32_t flags) in MXC_I2S_RevA_DisableInt() argument
449 i2s->inten &= ~flags; in MXC_I2S_RevA_DisableInt()
452 int MXC_I2S_RevA_GetFlags(mxc_i2s_reva_regs_t *i2s) in MXC_I2S_RevA_GetFlags() argument
454 return (i2s->intfl & 0xF); in MXC_I2S_RevA_GetFlags()
457 void MXC_I2S_RevA_ClearFlags(mxc_i2s_reva_regs_t *i2s, uint32_t flags) in MXC_I2S_RevA_ClearFlags() argument
459 i2s->intfl |= flags; in MXC_I2S_RevA_ClearFlags()
462 int MXC_I2S_RevA_Transaction(mxc_i2s_reva_regs_t *i2s, mxc_i2s_req_t *i2s_req) in MXC_I2S_RevA_Transaction() argument
474 i2s->ctrl1ch0 &= ~MXC_F_I2S_REVA_CTRL1CH0_EN; // Disable I2S while it's being configured in MXC_I2S_RevA_Transaction()
507 MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL, in MXC_I2S_RevA_Transaction()
513 i2s->ctrl1ch0 |= MXC_F_I2S_REVA_CTRL1CH0_EN; // Enable I2S RX/TX in MXC_I2S_RevA_Transaction()
516 MXC_I2S_RevA_Handler(i2s); in MXC_I2S_RevA_Transaction()
524 int MXC_I2S_RevA_TransactionAsync(mxc_i2s_reva_regs_t *i2s, mxc_i2s_req_t *i2s_req) in MXC_I2S_RevA_TransactionAsync() argument
537 i2s->ctrl1ch0 &= ~MXC_F_I2S_REVA_CTRL1CH0_EN; // Disable I2S while it's being configured in MXC_I2S_RevA_TransactionAsync()
573 MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL, in MXC_I2S_RevA_TransactionAsync()
583 i2s->ctrl1ch0 |= MXC_F_I2S_REVA_CTRL1CH0_EN; // Enable I2S RX/TX in MXC_I2S_RevA_TransactionAsync()
588 int MXC_I2S_RevA_TXDMAConfig(mxc_i2s_reva_regs_t *i2s, void *src_addr, int len) in MXC_I2S_RevA_TXDMAConfig() argument
597 i2s->dmach0 |= (2 << MXC_F_I2S_REVA_DMACH0_DMA_TX_THD_VAL_POS); //TX DMA Threshold in MXC_I2S_RevA_TXDMAConfig()
656 i2s->dmach0 |= MXC_F_I2S_REVA_DMACH0_DMA_TX_EN; //Enable I2S DMA in MXC_I2S_RevA_TXDMAConfig()
665 int MXC_I2S_RevA_RXDMAConfig(mxc_i2s_reva_regs_t *i2s, void *dest_addr, int len) in MXC_I2S_RevA_RXDMAConfig() argument
674 i2s->dmach0 |= (6 << MXC_F_I2S_REVA_DMACH0_DMA_RX_THD_VAL_POS); //RX DMA Threshold in MXC_I2S_RevA_RXDMAConfig()
733 i2s->dmach0 |= MXC_F_I2S_REVA_DMACH0_DMA_RX_EN; //Enable I2S DMA in MXC_I2S_RevA_RXDMAConfig()
742 void MXC_I2S_RevA_Handler(mxc_i2s_reva_regs_t *i2s) in MXC_I2S_RevA_Handler() argument
750 while (i2s->dmach0 & MXC_F_I2S_REVA_DMACH0_TX_LVL) {} in MXC_I2S_RevA_Handler()