80     MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_WSIZE,  in configure_data_sizes()
98         i2s->ctrl0ch0 |= (req->stereoMode << MXC_F_I2S_REVA_CTRL0CH0_STEREO_POS);  in MXC_I2S_RevA_Init()
102     i2s->ctrl0ch0 |= (2 << MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL_POS);  in MXC_I2S_RevA_Init()
105     MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_ALIGN,  in MXC_I2S_RevA_Init()
128     i2s->ctrl0ch0 = 0x00;  in MXC_I2S_RevA_Shutdown()
132     i2s->ctrl0ch0 |= MXC_F_I2S_REVA_CTRL0CH0_RST; //Reset channel  in MXC_I2S_RevA_Shutdown()
158     i2s->ctrl0ch0 &= ~MXC_F_I2S_REVA_CTRL0CH0_WSIZE;  in MXC_I2S_RevA_ConfigData()
214     MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_TX_EN,  in MXC_I2S_RevA_TXEnable()
220     MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_TX_EN,  in MXC_I2S_RevA_TXDisable()
226     MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_RX_EN,  in MXC_I2S_RevA_RXEnable()
232     MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_RX_EN,  in MXC_I2S_RevA_RXDisable()
242     i2s->ctrl0ch0 |= (threshold << MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL_POS);  in MXC_I2S_RevA_SetRXThreshold()
251     MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_CH_MODE,  in MXC_I2S_RevA_SetFrequency()
283     word_sz = (i2s->ctrl0ch0 & MXC_F_I2S_REVA_CTRL0CH0_WSIZE) >> MXC_F_I2S_REVA_CTRL0CH0_WSIZE_POS;  in MXC_I2S_RevA_GetSampleRate()
337     i2s->ctrl0ch0 |= MXC_F_I2S_REVA_CTRL0CH0_FLUSH;  in MXC_I2S_RevA_Flush()
339     while (i2s->ctrl0ch0 & MXC_F_I2S_REVA_CTRL0CH0_FLUSH) {}  in MXC_I2S_RevA_Flush()
507         MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL,  in MXC_I2S_RevA_Transaction()
573         MXC_SETFIELD(i2s->ctrl0ch0, MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL,  in MXC_I2S_RevA_TransactionAsync()