36 #define ASYNC_MODE (MXC_F_HTMR_REVA_CTRL_ACRE & htmr->ctrl)
44 int MXC_HTMR_RevA_Init(mxc_htmr_reva_regs_t *htmr, uint32_t sec, uint8_t ssec)  in MXC_HTMR_RevA_Init()  argument
46     if (htmr == NULL) {  in MXC_HTMR_RevA_Init()
50     if (MXC_HTMR_CheckBusy((mxc_htmr_regs_t *)htmr)) {  in MXC_HTMR_RevA_Init()
54     htmr->ctrl = MXC_F_HTMR_REVA_CTRL_WE; //  Allow Writes  in MXC_HTMR_RevA_Init()
56     if (MXC_HTMR_CheckBusy((mxc_htmr_regs_t *)htmr)) {  in MXC_HTMR_RevA_Init()
60     htmr->ctrl = HTMR_CTRL_RESET_DEFAULT; // Start with a Clean Register  in MXC_HTMR_RevA_Init()
62     if (MXC_HTMR_CheckBusy((mxc_htmr_regs_t *)htmr)) {  in MXC_HTMR_RevA_Init()
66     htmr->ctrl |= MXC_F_HTMR_REVA_CTRL_WE; // Set Write Enable, allow writing to reg.  in MXC_HTMR_RevA_Init()
68     if (MXC_HTMR_CheckBusy((mxc_htmr_regs_t *)htmr)) {  in MXC_HTMR_RevA_Init()
72     htmr->ssec = ssec;  in MXC_HTMR_RevA_Init()
74     if (MXC_HTMR_CheckBusy((mxc_htmr_regs_t *)htmr)) {  in MXC_HTMR_RevA_Init()
78     htmr->sec = sec;  in MXC_HTMR_RevA_Init()
80     if (MXC_HTMR_CheckBusy((mxc_htmr_regs_t *)htmr)) {  in MXC_HTMR_RevA_Init()
87         htmr->ctrl |= MXC_F_HTMR_REVA_CTRL_ACRE;  in MXC_HTMR_RevA_Init()
90     htmr->ctrl &= ~MXC_F_HTMR_REVA_CTRL_WE; // Prevent Writing...  in MXC_HTMR_RevA_Init()
95 int MXC_HTMR_RevA_Start(mxc_htmr_reva_regs_t *htmr)  in MXC_HTMR_RevA_Start()  argument
97     if (htmr == NULL) {  in MXC_HTMR_RevA_Start()
101     if (MXC_HTMR_CheckBusy((mxc_htmr_regs_t *)htmr)) {  in MXC_HTMR_RevA_Start()
105     htmr->ctrl |= MXC_F_HTMR_REVA_CTRL_WE; // Allow writing to registers  in MXC_HTMR_RevA_Start()
107     if (MXC_HTMR_CheckBusy((mxc_htmr_regs_t *)htmr)) {  in MXC_HTMR_RevA_Start()
112     htmr->ctrl |= MXC_F_HTMR_REVA_CTRL_HTEN; // setting RTCE = 1  in MXC_HTMR_RevA_Start()
114     if (MXC_HTMR_CheckBusy((mxc_htmr_regs_t *)htmr)) {  in MXC_HTMR_RevA_Start()
118     htmr->ctrl &= ~MXC_F_HTMR_REVA_CTRL_WE; // Prevent Writing...  in MXC_HTMR_RevA_Start()
123 int MXC_HTMR_RevA_Stop(mxc_htmr_reva_regs_t *htmr)  in MXC_HTMR_RevA_Stop()  argument
125     if (htmr == NULL) {  in MXC_HTMR_RevA_Stop()
129     if (MXC_HTMR_CheckBusy((mxc_htmr_regs_t *)htmr)) {  in MXC_HTMR_RevA_Stop()
133     htmr->ctrl |= MXC_F_HTMR_REVA_CTRL_WE; // Allow writing to registers  in MXC_HTMR_RevA_Stop()
135     if (MXC_HTMR_CheckBusy((mxc_htmr_regs_t *)htmr)) {  in MXC_HTMR_RevA_Stop()
140     htmr->ctrl &= ~MXC_F_HTMR_REVA_CTRL_HTEN; // setting RTCE = 0  in MXC_HTMR_RevA_Stop()
142     if (MXC_HTMR_CheckBusy((mxc_htmr_regs_t *)htmr)) {  in MXC_HTMR_RevA_Stop()
146     htmr->ctrl &= ~MXC_F_HTMR_REVA_CTRL_WE; // Prevent Writing...  in MXC_HTMR_RevA_Stop()
151 int MXC_HTMR_RevA_GetShortCount(mxc_htmr_reva_regs_t *htmr)  in MXC_HTMR_RevA_GetShortCount()  argument
153     if (htmr == NULL) {  in MXC_HTMR_RevA_GetShortCount()
159         if (MXC_HTMR_CheckBusy((mxc_htmr_regs_t *)htmr)) {  in MXC_HTMR_RevA_GetShortCount()
164     return htmr->ssec;  in MXC_HTMR_RevA_GetShortCount()
167 int MXC_HTMR_RevA_GetLongCount(mxc_htmr_reva_regs_t *htmr)  in MXC_HTMR_RevA_GetLongCount()  argument
169     if (htmr == NULL) {  in MXC_HTMR_RevA_GetLongCount()
175         if (MXC_HTMR_CheckBusy((mxc_htmr_regs_t *)htmr)) {  in MXC_HTMR_RevA_GetLongCount()
180     return htmr->sec;  in MXC_HTMR_RevA_GetLongCount()
183 int MXC_HTMR_RevA_SetLongAlarm(mxc_htmr_reva_regs_t *htmr, uint32_t ras)  in MXC_HTMR_RevA_SetLongAlarm()  argument
190     if (MXC_HTMR_DisableInt((mxc_htmr_regs_t *)htmr, MXC_F_HTMR_REVA_CTRL_ADE) == E_BUSY) {  in MXC_HTMR_RevA_SetLongAlarm()
194     if (MXC_HTMR_CheckBusy((mxc_htmr_regs_t *)htmr)) {  in MXC_HTMR_RevA_SetLongAlarm()
198     htmr->ras = (ras << MXC_F_HTMR_REVA_RAS_RAS_POS) & MXC_F_HTMR_REVA_RAS_RAS;  in MXC_HTMR_RevA_SetLongAlarm()
200     if (MXC_HTMR_EnableInt((mxc_htmr_regs_t *)htmr, MXC_F_HTMR_REVA_CTRL_ADE) == E_BUSY) {  in MXC_HTMR_RevA_SetLongAlarm()
207 int MXC_HTMR_RevA_SetShortAlarm(mxc_htmr_reva_regs_t *htmr, uint32_t rssa)  in MXC_HTMR_RevA_SetShortAlarm()  argument
209     if (MXC_HTMR_DisableInt((mxc_htmr_regs_t *)htmr, MXC_F_HTMR_REVA_CTRL_ASE) == E_BUSY) {  in MXC_HTMR_RevA_SetShortAlarm()
213     if (MXC_HTMR_CheckBusy((mxc_htmr_regs_t *)htmr)) {  in MXC_HTMR_RevA_SetShortAlarm()
217     htmr->rssa = (rssa << MXC_F_HTMR_REVA_RSSA_RSSA_POS) & MXC_F_HTMR_REVA_RSSA_RSSA;  in MXC_HTMR_RevA_SetShortAlarm()
219     if (MXC_HTMR_EnableInt((mxc_htmr_regs_t *)htmr, MXC_F_HTMR_REVA_CTRL_ASE) == E_BUSY) {  in MXC_HTMR_RevA_SetShortAlarm()
226 int MXC_HTMR_RevA_CheckBusy(mxc_htmr_reva_regs_t *htmr)  in MXC_HTMR_RevA_CheckBusy()  argument
230     while (htmr->ctrl & MXC_F_HTMR_CTRL_BUSY) {  in MXC_HTMR_RevA_CheckBusy()
241 int MXC_HTMR_RevA_GetFlags(mxc_htmr_reva_regs_t *htmr)  in MXC_HTMR_RevA_GetFlags()  argument
243     if (htmr == NULL) {  in MXC_HTMR_RevA_GetFlags()
247     return htmr->ctrl & MXC_HTMR_ALL_INT_FLAGS;  in MXC_HTMR_RevA_GetFlags()
250 int MXC_HTMR_RevA_ClearFlags(mxc_htmr_reva_regs_t *htmr, int flags)  in MXC_HTMR_RevA_ClearFlags()  argument
252     if (MXC_HTMR_CheckBusy((mxc_htmr_regs_t *)htmr)) {  in MXC_HTMR_RevA_ClearFlags()
256     htmr->ctrl &= ~(flags & MXC_HTMR_ALL_INT_FLAGS);  in MXC_HTMR_RevA_ClearFlags()
261 int MXC_HTMR_RevA_EnableInt(mxc_htmr_reva_regs_t *htmr, uint32_t mask)  in MXC_HTMR_RevA_EnableInt()  argument
263     if (MXC_HTMR_CheckBusy((mxc_htmr_regs_t *)htmr)) {  in MXC_HTMR_RevA_EnableInt()
267     htmr->ctrl |= (mask & MXC_HTMR_ALL_INT_ENABLES); // Disable Long Interval Interrupt  in MXC_HTMR_RevA_EnableInt()
269     if (MXC_HTMR_CheckBusy((mxc_htmr_regs_t *)htmr)) {  in MXC_HTMR_RevA_EnableInt()
276 int MXC_HTMR_RevA_DisableInt(mxc_htmr_reva_regs_t *htmr, uint32_t mask)  in MXC_HTMR_RevA_DisableInt()  argument
278     if (MXC_HTMR_CheckBusy((mxc_htmr_regs_t *)htmr)) {  in MXC_HTMR_RevA_DisableInt()
282     htmr->ctrl &= ~(mask & MXC_HTMR_ALL_INT_ENABLES); // Disable Long Interval Interrupt  in MXC_HTMR_RevA_DisableInt()
284     if (MXC_HTMR_CheckBusy((mxc_htmr_regs_t *)htmr)) {  in MXC_HTMR_RevA_DisableInt()