36 #define ASYNC_MODE (MXC_F_HTMR_REVA_CTRL_ACRE & htmr->ctrl)
54     htmr->ctrl = MXC_F_HTMR_REVA_CTRL_WE; //  Allow Writes  in MXC_HTMR_RevA_Init()
60     htmr->ctrl = HTMR_CTRL_RESET_DEFAULT; // Start with a Clean Register  in MXC_HTMR_RevA_Init()
66     htmr->ctrl |= MXC_F_HTMR_REVA_CTRL_WE; // Set Write Enable, allow writing to reg.  in MXC_HTMR_RevA_Init()
87         htmr->ctrl |= MXC_F_HTMR_REVA_CTRL_ACRE;  in MXC_HTMR_RevA_Init()
90     htmr->ctrl &= ~MXC_F_HTMR_REVA_CTRL_WE; // Prevent Writing...  in MXC_HTMR_RevA_Init()
105     htmr->ctrl |= MXC_F_HTMR_REVA_CTRL_WE; // Allow writing to registers  in MXC_HTMR_RevA_Start()
112     htmr->ctrl |= MXC_F_HTMR_REVA_CTRL_HTEN; // setting RTCE = 1  in MXC_HTMR_RevA_Start()
118     htmr->ctrl &= ~MXC_F_HTMR_REVA_CTRL_WE; // Prevent Writing...  in MXC_HTMR_RevA_Start()
133     htmr->ctrl |= MXC_F_HTMR_REVA_CTRL_WE; // Allow writing to registers  in MXC_HTMR_RevA_Stop()
140     htmr->ctrl &= ~MXC_F_HTMR_REVA_CTRL_HTEN; // setting RTCE = 0  in MXC_HTMR_RevA_Stop()
146     htmr->ctrl &= ~MXC_F_HTMR_REVA_CTRL_WE; // Prevent Writing...  in MXC_HTMR_RevA_Stop()
230     while (htmr->ctrl & MXC_F_HTMR_CTRL_BUSY) {  in MXC_HTMR_RevA_CheckBusy()
247     return htmr->ctrl & MXC_HTMR_ALL_INT_FLAGS;  in MXC_HTMR_RevA_GetFlags()
256     htmr->ctrl &= ~(flags & MXC_HTMR_ALL_INT_FLAGS);  in MXC_HTMR_RevA_ClearFlags()
267     htmr->ctrl |= (mask & MXC_HTMR_ALL_INT_ENABLES); // Disable Long Interval Interrupt  in MXC_HTMR_RevA_EnableInt()
282     htmr->ctrl &= ~(mask & MXC_HTMR_ALL_INT_ENABLES); // Disable Long Interval Interrupt  in MXC_HTMR_RevA_DisableInt()