Lines Matching full:y
1 CONFIG_ZTEST=y
3 CONFIG_ASSERT=y
5 CONFIG_ASSERT_VERBOSE=y
8 CONFIG_BT=y
9 CONFIG_BT_HCI=y
14 CONFIG_BT_LLL_VENDOR_NORDIC=y
16 CONFIG_BT_CENTRAL=y
17 CONFIG_BT_PERIPHERAL=y
18 CONFIG_BT_ISO_PERIPHERAL=y
19 CONFIG_BT_ISO_CENTRAL=y
20 CONFIG_BT_CTLR_PERIPHERAL_ISO=y
21 CONFIG_BT_CTLR_CENTRAL_ISO=y
23 CONFIG_BT_ASSERT=y
24 CONFIG_BT_CTLR_ASSERT_HANDLER=y
26 CONFIG_BT_CTLR_PER_INIT_FEAT_XCHG=y
27 CONFIG_BT_CTLR_SCA_UPDATE=y
28 CONFIG_BT_SCA_UPDATE=y
30 CONFIG_BT_PHY_UPDATE=y
31 CONFIG_BT_CTLR_PHY_2M=y
32 CONFIG_BT_CTLR_PHY_CODED=y
34 CONFIG_BT_DATA_LEN_UPDATE=y
37 CONFIG_BT_CTLR_DF=y
38 CONFIG_BT_CTLR_DF_CTE_TX=y
39 CONFIG_BT_CTLR_DF_CTE_RX_SAMPLE_1US=y
40 CONFIG_BT_CTLR_DF_ANT_SWITCH_1US=y
41 CONFIG_BT_CTLR_DF_CONN_CTE_RX=y
42 CONFIG_BT_CTLR_DF_CONN_CTE_TX=y
43 CONFIG_BT_CTLR_DF_CONN_CTE_REQ=y
44 CONFIG_BT_CTLR_DF_CONN_CTE_RSP=y
45 CONFIG_BT_CTLR_DF_ANT_SWITCH_TX=y
46 CONFIG_BT_CTLR_DF_CTE_RX=y