Lines Matching +full:cs +full:- +full:interval
2 * Copyright (c) 2018-2019 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
96 adv = ((struct lll_adv *)ftr->param)->hdr.parent;
97 conn = lll->hdr.parent;
100 pdu_adv = (void *)rx->pdu;
102 peer_addr_type = pdu_adv->tx_addr;
103 memcpy(peer_addr, pdu_adv->connect_ind.init_addr, BDADDR_SIZE);
106 uint8_t rl_idx = ftr->rl_idx;
123 link = rx->hdr.link;
127 const uint8_t own_id_addr_type = pdu_adv->rx_addr;
128 const uint8_t *own_id_addr = adv->own_id_addr;
133 invalid_release(&adv->ull, lll, link, rx);
139 conn->peer_id_addr_type = peer_id_addr_type;
140 (void)memcpy(conn->peer_id_addr, peer_id_addr,
141 sizeof(conn->peer_id_addr));
142 conn->own_id_addr_type = own_id_addr_type;
143 (void)memcpy(conn->own_id_addr, own_id_addr,
144 sizeof(conn->own_id_addr));
149 conn->past = ull_conn_default_past_param_get();
152 memcpy(&lll->crc_init[0], &pdu_adv->connect_ind.crc_init[0], 3);
153 memcpy(&lll->access_addr[0], &pdu_adv->connect_ind.access_addr[0], 4);
154 memcpy(&lll->data_chan_map[0], &pdu_adv->connect_ind.chan_map[0],
155 sizeof(lll->data_chan_map));
156 lll->data_chan_count = util_ones_count_get(&lll->data_chan_map[0],
157 sizeof(lll->data_chan_map));
158 lll->data_chan_hop = pdu_adv->connect_ind.hop;
159 lll->interval = sys_le16_to_cpu(pdu_adv->connect_ind.interval);
160 if ((lll->data_chan_count < CHM_USED_COUNT_MIN) ||
161 (lll->data_chan_hop < CHM_HOP_COUNT_MIN) ||
162 (lll->data_chan_hop > CHM_HOP_COUNT_MAX) ||
163 !lll->interval) {
164 invalid_release(&adv->ull, lll, link, rx);
169 ((struct lll_adv *)ftr->param)->conn = NULL;
171 lll->latency = sys_le16_to_cpu(pdu_adv->connect_ind.latency);
173 win_offset = sys_le16_to_cpu(pdu_adv->connect_ind.win_offset);
174 conn_interval_us = lll->interval * CONN_INT_UNIT_US;
182 } else if (adv->lll.aux) {
183 if (adv->lll.phy_s & PHY_CODED) {
193 /* Set LLCP as connection-wise connected */
197 conn->periph.sca = pdu_adv->connect_ind.sca;
198 lll->periph.window_widening_periodic_us =
200 lll_clock_ppm_get(conn->periph.sca)) *
202 lll->periph.window_widening_max_us = (conn_interval_us >> 1) -
204 lll->periph.window_size_event_us = pdu_adv->connect_ind.win_size *
208 conn->supervision_timeout = sys_le16_to_cpu(pdu_adv->connect_ind.timeout);
217 conn->connect_accept_to = conn_accept_timeout * 625U;
219 conn->connect_accept_to = DEFAULT_CONNECTION_ACCEPT_TIMEOUT_US;
224 conn->apto_reload = RADIO_CONN_EVENTS((30 * 1000 * 1000),
230 conn->appto_reload = (conn->apto_reload > (lll->latency + 6)) ?
231 (conn->apto_reload - (lll->latency + 6)) :
232 conn->apto_reload;
236 memcpy((void *)&conn->periph.force, &lll->access_addr[0],
237 sizeof(conn->periph.force));
242 } else if (adv->lll.aux) {
246 chan_sel = pdu_adv->chan_sel;
257 cc->status = 0U;
258 cc->role = 1U;
261 if (ull_filter_lll_lrpa_used(adv->lll.rl_idx)) {
262 memcpy(&cc->local_rpa[0], &pdu_adv->connect_ind.adv_addr[0],
265 memset(&cc->local_rpa[0], 0x0, BDADDR_SIZE);
270 memcpy(cc->peer_rpa, peer_addr, BDADDR_SIZE);
272 memset(cc->peer_rpa, 0x0, BDADDR_SIZE);
276 cc->peer_addr_type = peer_addr_type;
277 memcpy(cc->peer_addr, peer_id_addr, BDADDR_SIZE);
279 cc->interval = lll->interval;
280 cc->latency = lll->latency;
281 cc->timeout = conn->supervision_timeout;
282 cc->sca = conn->periph.sca;
284 lll->handle = ll_conn_handle_get(conn);
285 rx->hdr.handle = lll->handle;
288 lll->tx_pwr_lvl = RADIO_TXP_DEFAULT;
294 struct node_rx_cs *cs; local
299 rx_csa = (void *)ftr->extra;
306 link = rx->hdr.link;
308 rx->hdr.handle = lll->handle;
309 rx->hdr.type = NODE_RX_TYPE_CHAN_SEL_ALGO;
311 cs = (void *)rx_csa->pdu;
314 lll->data_chan_sel = 1;
315 lll->data_chan_id = lll_chan_id(lll->access_addr);
317 cs->csa = 0x01;
319 cs->csa = 0x00;
333 rx = adv->lll.node_rx_adv_term;
334 link = rx->hdr.link;
339 rx->hdr.type = NODE_RX_TYPE_EXT_ADV_TERMINATE;
340 rx->hdr.handle = handle;
341 rx->rx_ftr.param_adv_term.status = 0U;
342 rx->rx_ftr.param_adv_term.conn_handle = lll->handle;
343 rx->rx_ftr.param_adv_term.num_events = 0U;
352 max_tx_time = lll->dle.eff.max_tx_time;
353 max_rx_time = lll->dle.eff.max_rx_time;
366 PDU_DC_MAX_US(PDU_DC_PAYLOAD_SIZE_MIN, lll->phy_tx));
368 PDU_DC_MAX_US(PDU_DC_PAYLOAD_SIZE_MIN, lll->phy_rx));
374 max_tx_time = PDU_MAX_US(0U, 0U, lll->phy_tx);
375 max_rx_time = PDU_MAX_US(0U, 0U, lll->phy_rx);
384 ready_delay_us = lll_radio_rx_ready_delay_get(lll->phy_rx, PHY_FLAGS_S8);
389 lll->tifs_tx_us = EVENT_IFS_DEFAULT_US;
390 lll->tifs_rx_us = EVENT_IFS_DEFAULT_US;
391 lll->tifs_hcto_us = EVENT_IFS_DEFAULT_US;
392 lll->tifs_cis_us = EVENT_IFS_DEFAULT_US;
396 slot_us += lll->tifs_rx_us + (EVENT_CLOCK_JITTER_US << 1);
404 conn->ull.ticks_active_to_start = 0U;
405 conn->ull.ticks_prepare_to_start =
407 conn->ull.ticks_preempt_to_start =
409 conn->ull.ticks_slot = HAL_TICKER_US_TO_TICKS_CEIL(slot_us);
411 ticks_slot_offset = MAX(conn->ull.ticks_active_to_start,
412 conn->ull.ticks_prepare_to_start);
420 conn_interval_us -= lll->periph.window_widening_periodic_us;
422 conn_offset_us = ftr->radio_end_us;
425 conn_offset_us -= EVENT_TICKER_RES_MARGIN_US;
426 conn_offset_us -= EVENT_JITTER_US;
427 conn_offset_us -= ready_delay_us;
437 struct lll_adv_aux *lll_aux = adv->lll.aux;
452 aux->is_started = 0U;
458 ticks_at_stop = ftr->ticks_anchor +
459 HAL_TICKER_US_TO_TICKS(conn_offset_us) -
468 if (adv->lll.is_hdcd) {
482 ftr->ticks_anchor - ticks_slot_offset,
487 (conn->ull.ticks_slot +
505 if (conn->lll.latency_event && !conn->periph.latency_cancel) {
508 conn->periph.latency_cancel = 1U;
539 if (unlikely(conn->lll.handle == 0xFFFF)) {
545 conn->common.is_must_expire = (lazy == TICKER_LAZY_MUST_EXPIRE);
547 /* If this is a must-expire callback, LLCP state machine does not need
559 * active radio event which will re-enable
574 ref = ull_ref_inc(&conn->ull);
582 p.param = &conn->lll;
590 /* De-mux remaining tx nodes from FIFO */
624 hdr->disabled_cb = NULL;
627 lll->periph.initiated = 0U;
630 rx->hdr.type = NODE_RX_TYPE_RELEASE;
639 rx_csa = rx->rx_ftr.extra;
646 link = rx->hdr.link;
649 rx->hdr.type = NODE_RX_TYPE_RELEASE;
676 conn->periph.latency_cancel = 0U;
690 if (!conn->lll.role) {