Lines Matching +full:48 +full:- +full:49
4 * SPDX-License-Identifier: Apache-2.0
156 #define MIO48 48
157 #define MIO49 49
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
196 #define MIO_GROUP_SPI1_3_GRP_PINS 46, 47, 48
197 #define MIO_GROUP_SPI1_3_SS0_PINS 49
206 #define MIO_GROUP_SDIO1_3_GRP_PINS 46, 47, 48, 49, 50, 51
239 #define MIO_GROUP_CAN1_10_GRP_PINS 48, 49
262 #define MIO_GROUP_UART1_10_GRP_PINS 48, 49
284 #define MIO_GROUP_I2C1_9_GRP_PINS 48, 49
345 #define MIO_GROUP_GPIO0_48_GRP_PINS 48
346 #define MIO_GROUP_GPIO0_49_GRP_PINS 49
352 #define MIO_GROUP_USB1_0_GRP_PINS 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51
360 /* Iterate over each pinctrl-n phandle child */
367 * - Iterate over each pin in group and populate pinctrl_soc_pin_t
369 * - Iterate over each pin in pins and populate pinctrl_soc_pin_t