Lines Matching +full:42 +full:- +full:43

4  * SPDX-License-Identifier: Apache-2.0
150 #define MIO42 42
151 #define MIO43 43
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
181 #define MIO_GROUP_SPI0_2_SS0_PINS          42
182 #define MIO_GROUP_SPI0_2_SS1_PINS          43
202 #define MIO_GROUP_SDIO0_2_GRP_PINS         40, 41, 42, 43, 44, 45
226 #define MIO_GROUP_CAN0_8_GRP_PINS          42, 43
249 #define MIO_GROUP_UART0_8_GRP_PINS         42, 43
272 #define MIO_GROUP_I2C0_8_GRP_PINS          42, 43
288 #define MIO_GROUP_TTC0_2_GRP_PINS          42, 43
339 #define MIO_GROUP_GPIO0_42_GRP_PINS        42
340 #define MIO_GROUP_GPIO0_43_GRP_PINS        43
352 #define MIO_GROUP_USB1_0_GRP_PINS          40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51
360 /* Iterate over each pinctrl-n phandle child */
367  *   - Iterate over each pin in group and populate pinctrl_soc_pin_t
369  *   - Iterate over each pin in pins and populate pinctrl_soc_pin_t