Lines Matching full:28
18 /* MIO_PIN_xx SLCR register fields (from Xilinx UG585 v1.13, B.28 SLCR) */
52 /* MIO pin function multiplexing (from Xilinx UG585 v1.13, B.28 SLCR) */
86 /* MIO SDIO CD/WP pin selection (from Xilinx UG585 v1.13, B.28 SLCR) */
136 #define MIO28 28
165 #define MIO_GROUP_ETHERNET1_0_GRP_PINS 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
176 #define MIO_GROUP_SPI0_1_GRP_PINS 28, 29, 33
201 #define MIO_GROUP_SDIO0_1_GRP_PINS 28, 29, 30, 31, 32, 33
213 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
234 #define MIO_GROUP_CAN1_5_GRP_PINS 28, 29
257 #define MIO_GROUP_UART1_5_GRP_PINS 28, 29
279 #define MIO_GROUP_I2C1_4_GRP_PINS 28, 29
290 #define MIO_GROUP_TTC1_1_GRP_PINS 28, 29
325 #define MIO_GROUP_GPIO0_28_GRP_PINS 28
351 #define MIO_GROUP_USB0_0_GRP_PINS 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39