Lines Matching +full:18 +full:- +full:50
4 * SPDX-License-Identifier: Apache-2.0
126 #define MIO18 18
158 #define MIO50 50
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
164 #define MIO_GROUP_ETHERNET0_0_GRP_PINS 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27
173 #define MIO_GROUP_SPI0_0_SS0_PINS 18
198 #define MIO_GROUP_SPI1_3_SS1_PINS 50
200 #define MIO_GROUP_SDIO0_0_GRP_PINS 16, 17, 18, 19, 20, 21
206 #define MIO_GROUP_SDIO1_3_GRP_PINS 46, 47, 48, 49, 50, 51
212 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \
217 12, 13, 14, 16, 17, 18, 19, 20, 21, 22, 23
220 #define MIO_GROUP_CAN0_2_GRP_PINS 18, 19
228 #define MIO_GROUP_CAN0_10_GRP_PINS 50, 51
243 #define MIO_GROUP_UART0_2_GRP_PINS 18, 19
251 #define MIO_GROUP_UART0_10_GRP_PINS 50, 51
266 #define MIO_GROUP_I2C0_2_GRP_PINS 18, 19
274 #define MIO_GROUP_I2C0_10_GRP_PINS 50, 51
286 #define MIO_GROUP_TTC0_0_GRP_PINS 18, 19
295 #define MIO_GROUP_SWDT0_3_GRP_PINS 50, 51
315 #define MIO_GROUP_GPIO0_18_GRP_PINS 18
347 #define MIO_GROUP_GPIO0_50_GRP_PINS 50
352 #define MIO_GROUP_USB1_0_GRP_PINS 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51
360 /* Iterate over each pinctrl-n phandle child */
367 * - Iterate over each pin in group and populate pinctrl_soc_pin_t
369 * - Iterate over each pin in pins and populate pinctrl_soc_pin_t