Lines Matching +full:extra +full:- +full:byte

2  * Copyright (c) 2013-2014 Wind River Systems, Inc.
3  * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>
8  * - include/arch/arm/cortex_m/scripts/linker.ld
9  * - include/arch/riscv/common/linker.ld
10  * - include/arch/riscv/pulpino/linker.ld
12  * SPDX-License-Identifier: Apache-2.0
18 #include <zephyr/linker/linker-defs.h>
19 #include <zephyr/linker/linker-tool.h>
22  * Extra efforts would need to be taken to ensure the IRQ handlers are within
23  * jumping distance of the vector table in non-XIP builds, so avoid them.
43 #define ROM_SIZE (DT_REG_SIZE(DT_CHOSEN(zephyr_code_partition)) - VECTOR_BASE)
52 #define ROM_SIZE (DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) - VECTOR_SIZE)
65      * Each RISC-V core on this chip (RI5CY and ZERO-RISCY) has
88 #include <zephyr/linker/rel-sections.ld>
91 #include <zephyr/linker/llext-sections.ld>
114 #include <snippets-rom-start.ld>
127 #include <zephyr/linker/common-rom.ld>
131 #include <snippets-rom-sections.ld>
132 #include <zephyr/linker/thread-local-storage.ld>
146 #include <snippets-rodata.ld>
150 #include <zephyr/linker/cplusplus-rom.ld>
156     /* The vector table goes into core-dependent flash locations. */
180 	/* https://groups.google.com/a/groups.riscv.org/d/msg/sw-dev/60IdaZj27dY/TKT3hbNlAgAJ */
187 #include <snippets-rwdata.ld>
192 	__data_size = __data_end - __data_start;
195 #include <zephyr/linker/common-ram.ld>
196 #include <zephyr/linker/cplusplus-ram.ld>
201 #include <snippets-data-sections.ld>
209 	 * For performance, BSS section is assumed to be 4 byte aligned and
219 	 /* Ensure 4 byte alignment for the entire section. */
227 	 * This section is used for non-initialized objects that
235 #include <snippets-noinit.ld>
242 #include <snippets-ram-sections.ld>
247 #include <snippets-sections.ld>
249 #include <zephyr/linker/ram-end.ld>
254 /* Bogus section, post-processed during the build to initialize interrupts. */
258 #include <zephyr/linker/debug-sections.ld>