2  * Copyright 2022-2024 NXP
4  * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/pinctrl/nxp-s32-pinctrl.h>
16 #define SIUL2_MSCR_SSS_MASK GENMASK(3, 0)
17 #define SIUL2_MSCR_SSS(v)   FIELD_PREP(SIUL2_MSCR_SSS_MASK, (v))  argument
19 #define SIUL2_MSCR_SMC(v)   FIELD_PREP(SIUL2_MSCR_SMC_MASK, (v))  argument
21 #define SIUL2_MSCR_IFE(v)   FIELD_PREP(SIUL2_MSCR_IFE_MASK, (v))  argument
22 #define SIUL2_MSCR_DSE_MASK BIT(8)
23 #define SIUL2_MSCR_DSE(v)   FIELD_PREP(SIUL2_MSCR_DSE_MASK, (v))  argument
25 #define SIUL2_MSCR_PUS(v)   FIELD_PREP(SIUL2_MSCR_PUS_MASK, (v))  argument
27 #define SIUL2_MSCR_PUE(v)   FIELD_PREP(SIUL2_MSCR_PUE_MASK, (v))  argument
29 #define SIUL2_MSCR_SRC(v)   FIELD_PREP(SIUL2_MSCR_SRC_MASK, (v))  argument
31 #define SIUL2_MSCR_PKE(v)   FIELD_PREP(SIUL2_MSCR_PKE_MASK, (v))  argument
33 #define SIUL2_MSCR_INV(v)   FIELD_PREP(SIUL2_MSCR_INV_MASK, (v))  argument
35 #define SIUL2_MSCR_IBE(v)   FIELD_PREP(SIUL2_MSCR_IBE_MASK, (v))  argument
37 #define SIUL2_MSCR_OBE(v)   FIELD_PREP(SIUL2_MSCR_OBE_MASK, (v))  argument
39 #define SIUL2_IMCR_SSS_MASK GENMASK(3, 0)
40 #define SIUL2_IMCR_SSS(v)   FIELD_PREP(SIUL2_IMCR_SSS_MASK, (v))  argument