4  * SPDX-License-Identifier: Apache-2.0
40 /* Partition p Process Configuration Register */
41 #define MC_ME_PRTN_PCONF(p)             (0x100 + 0x200 * (p))  argument
44 /* Partition p Process Update Register */
45 #define MC_ME_PRTN_PUPD(p)              (0x104 + 0x200 * (p))  argument
48 /* Partition p Status Register */
49 #define MC_ME_PRTN_STAT(p)              (0x108 + 0x200 * (p))  argument
52 /* Partition p COFB c Clock Status Register */
53 #define MC_ME_PRTN_COFB_STAT(p, c)      (0x110 + 0x200 * (p) + 0x4 * (c))  argument
54 /* Partition p COFB c Clock Enable Register */
55 #define MC_ME_PRTN_COFB_CLKEN(p, c)     (0x130 + 0x200 * (p) + 0x4 * (c))  argument
56 /* Partition p Core c Process Configuration Register */
57 #define MC_ME_PRTN_CORE_PCONF(p, c)     (0x140 + 0x200 * (p) + 0x20 * (c))  argument
61 #define MC_ME_PRTN_CORE_PUPD(p, c)      (0x144 + 0x200 * (p) + 0x20 * (c))  argument
65 #define MC_ME_PRTN_CORE_STAT(p, c)      (0x148 + 0x200 * (p) + 0x20 * (c))  argument
71 #define MC_ME_PRTN_CORE_ADDR(p, c)      (0x14c + 0x200 * (p) + 0x20 * (c))  argument
117 		err = -ENOTSUP;  in mc_me_set_mode()
128  * - Leads most parts of the chip, except a few modules, to reset. SRAM content
130  * - Flash is always reset, so an updated value of the option bits is reloaded
132  * - Trimming is lost.
133  * - STCU is reset and configured BISTs are executed.
136  * - Leads all the communication peripherals and cores to reset. The communication
140  * - The volatile registers are not reset; in case of a reset event, the
142  * - No BISTs are executed after functional reset.