Lines Matching refs:IOMUX_FSEL_CLR
20 #define IOMUX_FSEL_CLR(mask) ((mask) << 13) macro
91 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \
98 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \
105 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \
112 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \
119 IOMUX_FSEL_CLR(0x800000ULL) | /* FSEL bits to clear */ \
126 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \
133 IOMUX_FSEL_CLR(0x1000000ULL) | /* FSEL bits to clear */ \
140 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \
147 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \
154 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \
161 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \
168 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \
175 IOMUX_FSEL_CLR(0x8020ULL) | /* FSEL bits to clear */ \
182 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \
189 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \
196 IOMUX_FSEL_CLR(0x8600ULL) | /* FSEL bits to clear */ \
203 IOMUX_FSEL_CLR(0x8600ULL) | /* FSEL bits to clear */ \
210 IOMUX_FSEL_CLR(0x8600ULL) | /* FSEL bits to clear */ \
217 IOMUX_FSEL_CLR(0xc600ULL) | /* FSEL bits to clear */ \
224 IOMUX_FSEL_CLR(0x8000ULL) | /* FSEL bits to clear */ \
231 IOMUX_FSEL_CLR(0x8000ULL) | /* FSEL bits to clear */ \
238 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \
245 IOMUX_FSEL_CLR(0x4000000ULL) | /* FSEL bits to clear */ \
252 IOMUX_FSEL_CLR(0x4000000ULL) | /* FSEL bits to clear */ \
259 IOMUX_FSEL_CLR(0x40000000ULL) | /* FSEL bits to clear */ \
266 IOMUX_FSEL_CLR(0x10000ULL) | /* FSEL bits to clear */ \
273 IOMUX_FSEL_CLR(0x80000000ULL) | /* FSEL bits to clear */ \
280 IOMUX_FSEL_CLR(0x10000000ULL) | /* FSEL bits to clear */ \
287 IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
294 IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
301 IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
308 IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
315 IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
322 IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
329 IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
336 IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \
343 IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \
350 IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \
357 IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \
364 IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \
371 IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \
378 IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \
385 IOMUX_FSEL_CLR(0x800ULL) | /* FSEL bits to clear */ \
392 IOMUX_FSEL_CLR(0x800ULL) | /* FSEL bits to clear */ \
399 IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \
406 IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \
413 IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \
420 IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \
427 IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \
434 IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \
441 IOMUX_FSEL_CLR(0x22000ULL) | /* FSEL bits to clear */ \
448 IOMUX_FSEL_CLR(0x40810ULL) | /* FSEL bits to clear */ \
455 IOMUX_FSEL_CLR(0x80810ULL) | /* FSEL bits to clear */ \
462 IOMUX_FSEL_CLR(0x100810ULL) | /* FSEL bits to clear */ \
469 IOMUX_FSEL_CLR(0x200810ULL) | /* FSEL bits to clear */ \
476 IOMUX_FSEL_CLR(0x400000ULL) | /* FSEL bits to clear */ \
483 IOMUX_FSEL_CLR(0x8000800ULL) | /* FSEL bits to clear */ \
490 IOMUX_FSEL_CLR(0x8000800ULL) | /* FSEL bits to clear */ \
497 IOMUX_FSEL_CLR(0x2000000ULL) | /* FSEL bits to clear */ \
504 IOMUX_FSEL_CLR(0x2000000ULL) | /* FSEL bits to clear */ \
511 IOMUX_FSEL_CLR(0x2000000ULL) | /* FSEL bits to clear */ \
518 IOMUX_FSEL_CLR(0x20000000ULL) | /* FSEL bits to clear */ \
525 IOMUX_FSEL_CLR(0x4000000ULL) | /* FSEL bits to clear */ \
532 IOMUX_FSEL_CLR(0x4000000ULL) | /* FSEL bits to clear */ \