Lines Matching full:clear
85 * GPIO mux options. These options are used to clear all alternate
90 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x418ULL) | /* Flexcomm bits to clear */ \
91 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \
92 IOMUX_CTIMER_CLR(0ULL, 1ULL) | /* CTIMER offset to clear */ \
93 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
94 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
97 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
98 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \
99 IOMUX_CTIMER_CLR(1ULL, 1ULL) | /* CTIMER offset to clear */ \
100 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
101 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
104 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x32eULL) | /* Flexcomm bits to clear */ \
105 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \
106 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
107 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
108 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
111 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x22eULL) | /* Flexcomm bits to clear */ \
112 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \
113 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
114 IOMUX_SCTIMER_IN_CLR(0ULL, 1ULL) | /* SCTIMER input offset to clear */ \
115 IOMUX_SCTIMER_OUT_CLR(0ULL, 1ULL)) /* SCTIMER output offset to clear */
118 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x2dULL) | /* Flexcomm bits to clear */ \
119 IOMUX_FSEL_CLR(0x800000ULL) | /* FSEL bits to clear */ \
120 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
121 IOMUX_SCTIMER_IN_CLR(1ULL, 1ULL) | /* SCTIMER input offset to clear */ \
122 IOMUX_SCTIMER_OUT_CLR(1ULL, 1ULL)) /* SCTIMER output offset to clear */
125 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x430ULL) | /* Flexcomm bits to clear */ \
126 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \
127 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
128 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
129 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
132 (IOMUX_FLEXCOMM_CLR(0x1ULL, 0x418ULL) | /* Flexcomm bits to clear */ \
133 IOMUX_FSEL_CLR(0x1000000ULL) | /* FSEL bits to clear */ \
134 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
135 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
136 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
139 (IOMUX_FLEXCOMM_CLR(0x1ULL, 0xedULL) | /* Flexcomm bits to clear */ \
140 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \
141 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
142 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
143 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
146 (IOMUX_FLEXCOMM_CLR(0x1ULL, 0x2eeULL) | /* Flexcomm bits to clear */ \
147 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \
148 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
149 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
150 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
153 (IOMUX_FLEXCOMM_CLR(0x1ULL, 0x3eeULL) | /* Flexcomm bits to clear */ \
154 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \
155 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
156 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
157 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
160 (IOMUX_FLEXCOMM_CLR(0x1ULL, 0x430ULL) | /* Flexcomm bits to clear */ \
161 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \
162 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
163 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
164 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
167 (IOMUX_FLEXCOMM_CLR(0x1ULL, 0x40ULL) | /* Flexcomm bits to clear */ \
168 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \
169 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
170 IOMUX_SCTIMER_IN_CLR(8ULL, 1ULL) | /* SCTIMER input offset to clear */ \
171 IOMUX_SCTIMER_OUT_CLR(8ULL, 1ULL)) /* SCTIMER output offset to clear */
174 (IOMUX_FLEXCOMM_CLR(0x1ULL, 0x80ULL) | /* Flexcomm bits to clear */ \
175 IOMUX_FSEL_CLR(0x8020ULL) | /* FSEL bits to clear */ \
176 IOMUX_CTIMER_CLR(2ULL, 1ULL) | /* CTIMER offset to clear */ \
177 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
178 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
181 (IOMUX_FLEXCOMM_CLR(0x2ULL, 0x3eeULL) | /* Flexcomm bits to clear */ \
182 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \
183 IOMUX_CTIMER_CLR(3ULL, 1ULL) | /* CTIMER offset to clear */ \
184 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
185 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
188 (IOMUX_FLEXCOMM_CLR(0x2ULL, 0x2eeULL) | /* Flexcomm bits to clear */ \
189 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \
190 IOMUX_CTIMER_CLR(4ULL, 1ULL) | /* CTIMER offset to clear */ \
191 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
192 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
195 (IOMUX_FLEXCOMM_CLR(0x2ULL, 0xedULL) | /* Flexcomm bits to clear */ \
196 IOMUX_FSEL_CLR(0x8600ULL) | /* FSEL bits to clear */ \
197 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
198 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
199 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
202 (IOMUX_FLEXCOMM_CLR(0x2ULL, 0x418ULL) | /* Flexcomm bits to clear */ \
203 IOMUX_FSEL_CLR(0x8600ULL) | /* FSEL bits to clear */ \
204 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
205 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
206 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
209 (IOMUX_FLEXCOMM_CLR(0x2ULL, 0x430ULL) | /* Flexcomm bits to clear */ \
210 IOMUX_FSEL_CLR(0x8600ULL) | /* FSEL bits to clear */ \
211 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
212 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
213 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
216 (IOMUX_FLEXCOMM_CLR(0x2ULL, 0x80ULL) | /* Flexcomm bits to clear */ \
217 IOMUX_FSEL_CLR(0xc600ULL) | /* FSEL bits to clear */ \
218 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
219 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
220 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
223 (IOMUX_FLEXCOMM_CLR(0x3ULL, 0x430ULL) | /* Flexcomm bits to clear */ \
224 IOMUX_FSEL_CLR(0x8000ULL) | /* FSEL bits to clear */ \
225 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
226 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
227 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
230 (IOMUX_FLEXCOMM_CLR(0x3ULL, 0x418ULL) | /* Flexcomm bits to clear */ \
231 IOMUX_FSEL_CLR(0x8000ULL) | /* FSEL bits to clear */ \
232 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
233 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
234 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
237 (IOMUX_FLEXCOMM_CLR(0x2ULL, 0x40ULL) | /* Flexcomm bits to clear */ \
238 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \
239 IOMUX_CTIMER_CLR(5ULL, 1ULL) | /* CTIMER offset to clear */ \
240 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
241 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
244 (IOMUX_FLEXCOMM_CLR(0x3ULL, 0x40ULL) | /* Flexcomm bits to clear */ \
245 IOMUX_FSEL_CLR(0x4000000ULL) | /* FSEL bits to clear */ \
246 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
247 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
248 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
251 (IOMUX_FLEXCOMM_CLR(0x3ULL, 0x80ULL) | /* Flexcomm bits to clear */ \
252 IOMUX_FSEL_CLR(0x4000000ULL) | /* FSEL bits to clear */ \
253 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
254 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
255 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
258 (IOMUX_FLEXCOMM_CLR(0x3ULL, 0x3eeULL) | /* Flexcomm bits to clear */ \
259 IOMUX_FSEL_CLR(0x40000000ULL) | /* FSEL bits to clear */ \
260 IOMUX_CTIMER_CLR(6ULL, 1ULL) | /* CTIMER offset to clear */ \
261 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
262 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
265 (IOMUX_FLEXCOMM_CLR(0x3ULL, 0xedULL) | /* Flexcomm bits to clear */ \
266 IOMUX_FSEL_CLR(0x10000ULL) | /* FSEL bits to clear */ \
267 IOMUX_CTIMER_CLR(7ULL, 1ULL) | /* CTIMER offset to clear */ \
268 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
269 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
272 (IOMUX_FLEXCOMM_CLR(0x3ULL, 0x2eeULL) | /* Flexcomm bits to clear */ \
273 IOMUX_FSEL_CLR(0x80000000ULL) | /* FSEL bits to clear */ \
274 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
275 IOMUX_SCTIMER_IN_CLR(4ULL, 1ULL) | /* SCTIMER input offset to clear */ \
276 IOMUX_SCTIMER_OUT_CLR(4ULL, 1ULL)) /* SCTIMER output offset to clear */
279 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
280 IOMUX_FSEL_CLR(0x10000000ULL) | /* FSEL bits to clear */ \
281 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
282 IOMUX_SCTIMER_IN_CLR(5ULL, 1ULL) | /* SCTIMER input offset to clear */ \
283 IOMUX_SCTIMER_OUT_CLR(5ULL, 1ULL)) /* SCTIMER output offset to clear */
286 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
287 IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
288 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
289 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
290 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
293 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
294 IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
295 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
296 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
297 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
300 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
301 IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
302 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
303 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
304 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
307 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
308 IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
309 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
310 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
311 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
314 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
315 IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
316 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
317 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
318 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
321 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
322 IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
323 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
324 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
325 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
328 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
329 IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
330 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
331 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
332 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
335 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
336 IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \
337 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
338 IOMUX_SCTIMER_IN_CLR(6ULL, 1ULL) | /* SCTIMER input offset to clear */ \
339 IOMUX_SCTIMER_OUT_CLR(6ULL, 1ULL)) /* SCTIMER output offset to clear */
342 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
343 IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \
344 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
345 IOMUX_SCTIMER_IN_CLR(7ULL, 1ULL) | /* SCTIMER input offset to clear */ \
346 IOMUX_SCTIMER_OUT_CLR(7ULL, 1ULL)) /* SCTIMER output offset to clear */
349 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
350 IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \
351 IOMUX_CTIMER_CLR(8ULL, 1ULL) | /* CTIMER offset to clear */ \
352 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
353 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
356 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
357 IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \
358 IOMUX_CTIMER_CLR(9ULL, 1ULL) | /* CTIMER offset to clear */ \
359 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
360 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
363 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
364 IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \
365 IOMUX_CTIMER_CLR(10ULL, 1ULL) | /* CTIMER offset to clear */ \
366 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
367 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
370 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
371 IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \
372 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
373 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
374 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
377 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
378 IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \
379 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
380 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
381 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
384 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
385 IOMUX_FSEL_CLR(0x800ULL) | /* FSEL bits to clear */ \
386 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
387 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
388 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
391 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
392 IOMUX_FSEL_CLR(0x800ULL) | /* FSEL bits to clear */ \
393 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
394 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
395 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
398 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
399 IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \
400 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
401 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
402 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
405 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
406 IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \
407 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
408 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
409 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
412 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
413 IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \
414 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
415 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
416 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
419 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
420 IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \
421 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
422 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
423 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
426 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
427 IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \
428 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
429 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
430 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
433 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
434 IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \
435 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
436 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
437 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
440 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
441 IOMUX_FSEL_CLR(0x22000ULL) | /* FSEL bits to clear */ \
442 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
443 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
444 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
447 (IOMUX_FLEXCOMM_CLR(0x6ULL, 0x40ULL) | /* Flexcomm bits to clear */ \
448 IOMUX_FSEL_CLR(0x40810ULL) | /* FSEL bits to clear */ \
449 IOMUX_CTIMER_CLR(11ULL, 1ULL) | /* CTIMER offset to clear */ \
450 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
451 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
454 (IOMUX_FLEXCOMM_CLR(0x6ULL, 0x80ULL) | /* Flexcomm bits to clear */ \
455 IOMUX_FSEL_CLR(0x80810ULL) | /* FSEL bits to clear */ \
456 IOMUX_CTIMER_CLR(12ULL, 1ULL) | /* CTIMER offset to clear */ \
457 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
458 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
461 (IOMUX_FLEXCOMM_CLR(0x6ULL, 0x418ULL) | /* Flexcomm bits to clear */ \
462 IOMUX_FSEL_CLR(0x100810ULL) | /* FSEL bits to clear */ \
463 IOMUX_CTIMER_CLR(13ULL, 1ULL) | /* CTIMER offset to clear */ \
464 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
465 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
468 (IOMUX_FLEXCOMM_CLR(0x6ULL, 0xedULL) | /* Flexcomm bits to clear */ \
469 IOMUX_FSEL_CLR(0x200810ULL) | /* FSEL bits to clear */ \
470 IOMUX_CTIMER_CLR(14ULL, 1ULL) | /* CTIMER offset to clear */ \
471 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
472 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
475 (IOMUX_FLEXCOMM_CLR(0x6ULL, 0x430ULL) | /* Flexcomm bits to clear */ \
476 IOMUX_FSEL_CLR(0x400000ULL) | /* FSEL bits to clear */ \
477 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
478 IOMUX_SCTIMER_IN_CLR(9ULL, 1ULL) | /* SCTIMER input offset to clear */ \
479 IOMUX_SCTIMER_OUT_CLR(9ULL, 1ULL)) /* SCTIMER output offset to clear */
482 (IOMUX_FLEXCOMM_CLR(0x6ULL, 0x2eeULL) | /* Flexcomm bits to clear */ \
483 IOMUX_FSEL_CLR(0x8000800ULL) | /* FSEL bits to clear */ \
484 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
485 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
486 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
489 (IOMUX_FLEXCOMM_CLR(0x6ULL, 0x3eeULL) | /* Flexcomm bits to clear */ \
490 IOMUX_FSEL_CLR(0x8000800ULL) | /* FSEL bits to clear */ \
491 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
492 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
493 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
496 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
497 IOMUX_FSEL_CLR(0x2000000ULL) | /* FSEL bits to clear */ \
498 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
499 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
500 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
503 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
504 IOMUX_FSEL_CLR(0x2000000ULL) | /* FSEL bits to clear */ \
505 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
506 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
507 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
510 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
511 IOMUX_FSEL_CLR(0x2000000ULL) | /* FSEL bits to clear */ \
512 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
513 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
514 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
517 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
518 IOMUX_FSEL_CLR(0x20000000ULL) | /* FSEL bits to clear */ \
519 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
520 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
521 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
524 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
525 IOMUX_FSEL_CLR(0x4000000ULL) | /* FSEL bits to clear */ \
526 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
527 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
528 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
531 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
532 IOMUX_FSEL_CLR(0x4000000ULL) | /* FSEL bits to clear */ \
533 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
534 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
535 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */