Lines Matching +full:can +full:- +full:transceiver +full:- +full:gpio
2 * Copyright (c) 2014-2015 Wind River Systems, Inc.
6 * SPDX-License-Identifier: Apache-2.0
33 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
74 * @brief Initialize radio transceiver clock output
76 * The clock output of the transceiver can be used as an input clock
79 * output of the transceiver at 4 MHz. The default frequency of the CLK_OUT
80 * depends on the state of GPIO5 during transceiver reset. The frequency
87 SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK; in set_modem_clock()
88 /* Set PORTB.19 as output - modem RESET pin */ in set_modem_clock()
89 GPIOB->PDDR |= 0x00080000u; in set_modem_clock()
90 /* Set PORTC.0 as output - modem GPIO5 pin */ in set_modem_clock()
91 GPIOC->PDDR |= 0x00000001u; in set_modem_clock()
92 /* PORTB.19 as GPIO */ in set_modem_clock()
93 PORTB->PCR[19] = (PORTB->PCR[19] & ~PORT_PCR_MUX_MASK) | in set_modem_clock()
95 /* PORTC.0 as GPIO */ in set_modem_clock()
96 PORTC->PCR[0] = (PORTC->PCR[0] & ~PORT_PCR_MUX_MASK) | in set_modem_clock()
99 GPIOC->PCOR = 0x00000001u; in set_modem_clock()
101 GPIOB->PCOR = 0x00080000u; in set_modem_clock()
103 GPIOB->PSOR = 0x00080000u; in set_modem_clock()
153 PMC->REGSC |= PMC_REGSC_ACKISO_MASK; in soc_early_init_hook()