Lines Matching +full:divide +full:- +full:10
4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/linker/linker-defs.h>
24 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
49 /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */
60 /* Enable Sys Pll1 divide-by-2 clock or not */
62 /* Enable Sys Pll1 divide-by-5 clock or not */
129 ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | in clock_init()
135 (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) { in clock_init()
233 rootCfg.div = 10; in clock_init()
322 rootCfg.div = 10; in clock_init()
342 rootCfg.div = 10; in clock_init()
346 BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= in clock_init()
348 BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= in clock_init()
350 BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= in clock_init()
352 BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= in clock_init()
354 BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= in clock_init()
358 BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG |= in clock_init()
457 rootCfg.div = 10; in clock_init()
464 rootCfg.div = 10; in clock_init()
471 CCM->LPCG[1].LPM0 = 0x33333333; in clock_init()
472 CCM->LPCG[1].LPM1 = 0x33333333; in clock_init()
485 BLK_CTRL_S_AONMIX->M7_CFG |= BLK_CTRL_S_AONMIX_M7_CFG_TCM_SIZE_MASK; in clock_init()