181 	/* Configure M7 using ARM_PLL_CLK */  in clock_init()
188 	/* Configure M33 using SYS_PLL3_CLK */  in clock_init()
194 	/* Configure BUS_AON using SYS_PLL2_CLK */  in clock_init()
199 	/* Configure BUS_WAKEUP using SYS_PLL2_CLK */  in clock_init()
204 	/* Configure WAKEUP_AXI using SYS_PLL3_CLK */  in clock_init()
209 	/* Configure SWO_TRACE using SYS_PLL3_DIV2_CLK */  in clock_init()
215 	/* Configure M33_SYSTICK using OSC_24M */  in clock_init()
222 	/* Configure M7_SYSTICK using OSC_24M */  in clock_init()
231 	/* Configure LPUART0102 using SYS_PLL3_DIV2_CLK */  in clock_init()
239 	/* Configure LPI2C0102 using SYS_PLL3_DIV2_CLK */  in clock_init()
248 	/* Configure LPI2C0304 using SYS_PLL3_DIV2_CLK */  in clock_init()
257 	/* Configure LPI2C0506 using SYS_PLL3_DIV2_CLK */  in clock_init()
266 	/* Configure LPSPI0102 using SYS_PLL3_PFD1_CLK */  in clock_init()
275 	/* Configure GPT1 using SYS_PLL3_DIV2_CLK */  in clock_init()
282 	/* Configure GPT2 using SYS_PLL3_DIV2_CLK */  in clock_init()
296 	/* Configure ACMP using MuxSysPll3Out */  in clock_init()
305 	/* Configure ENET using SYS_PLL1_DIV2_CLK */  in clock_init()
310 	/* Configure TMR_1588 using SYS_PLL3_CLK */  in clock_init()
315 	/* Configure NETC using SYS_PLL3_PFD3_CLK */  in clock_init()
320 	/* Configure MAC0 using SYS_PLL1_DIV2_CLK */  in clock_init()
325 	/* Configure MAC1 using SYS_PLL1_DIV2_CLK */  in clock_init()
330 	/* Configure MAC2 using SYS_PLL1_DIV2_CLK */  in clock_init()
335 	/* Configure MAC3 using SYS_PLL1_DIV2_CLK */  in clock_init()
340 	/* Configure MAC4 using SYS_PLL1_DIV2_CLK */  in clock_init()
365 	/* Configure CAN1 using MuxSysPll3Out */  in clock_init()
372 	/* Configure CAN2 using MuxSysPll3Out */  in clock_init()
379 	/* Configure CAN3 using MuxSysPll3Out */  in clock_init()
390 	/* Configure LPTIMER1 using SYS_PLL3_DIV2_CLK */  in clock_init()
397 	/* Configure LPTIMER2 using SYS_PLL3_DIV2_CLK */  in clock_init()
404 	/* Configure LPTIMER3 using SYS_PLL3_DIV2_CLK */  in clock_init()
414 	/* Configure FLEXSPI1 using SYS_PLL3_PFD0_CLK */  in clock_init()
423 	/* Configure TPM2 using SYS_PLL3_DIV2_CLK */  in clock_init()
430 	/* Configure TPM4 using SYS_PLL3_DIV2_CLK */  in clock_init()
437 	/* Configure TPM5 using SYS_PLL3_DIV2_CLK */  in clock_init()
444 	/* Configure TPM6 using SYS_PLL3_DIV2_CLK */  in clock_init()
455 	/* Configure I3C1 using SYS_PLL3_DIV2_CLK */  in clock_init()
462 	/* Configure I3C2 using SYS_PLL3_DIV2_CLK */  in clock_init()