4  * SPDX-License-Identifier: Apache-2.0
19 #include "power.h"
28  * normal/full speed mode, low speed mode, and low power mode.
29  * If callbacks are present, the low power subsystem will disable
30  * PLLs for power savings when entering low power states.
34 	/* If run callback is set, low power must be as well. */  in imxrt_clock_pm_callbacks_register()
35 	__ASSERT_NO_MSG(callbacks && callbacks->clock_set_run && callbacks->clock_set_low_power);  in imxrt_clock_pm_callbacks_register()
36 	lpm_clock_hooks.clock_set_run = callbacks->clock_set_run;  in imxrt_clock_pm_callbacks_register()
37 	lpm_clock_hooks.clock_set_low_power = callbacks->clock_set_low_power;  in imxrt_clock_pm_callbacks_register()
38 	if (callbacks->clock_lpm_init) {  in imxrt_clock_pm_callbacks_register()
39 		lpm_clock_hooks.clock_lpm_init = callbacks->clock_lpm_init;  in imxrt_clock_pm_callbacks_register()
50 	 * ERR050143: CCM: When improper low-power sequence is used,  in lpm_set_sleep_mode_config()
51 	 * the SoC enters low power mode before the ARM core executes WFI.  in lpm_set_sleep_mode_config()
57 	 *      Low-Power mode.  in lpm_set_sleep_mode_config()
58 	 * 3) Software should mask IRQ #41 right after CCM Low-Power mode  in lpm_set_sleep_mode_config()
59 	 *      is set (set bits 0-1 of CCM_CLPCR).  in lpm_set_sleep_mode_config()
62 	clpcr = CCM->CLPCR & (~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK));  in lpm_set_sleep_mode_config()
75 	CCM->CLPCR = clpcr;  in lpm_set_sleep_mode_config()
81 	/* Enable the SNVS RTC as a wakeup source from soft-off mode, in case an RTC alarm  in lpm_enter_soft_off_mode()
85 	SNVS->LPCR |= SNVS_LPCR_TOP_MASK;  in lpm_enter_soft_off_mode()
93 	 * issue and disable interrupts using PRIMASK register as recommended  in lpm_enter_sleep_mode()
106 		SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;  in lpm_enter_sleep_mode()
109 		SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;  in lpm_enter_sleep_mode()
120 	CCM->CLPCR &= ~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK);  in lpm_set_run_mode_config()
128 		PMU->MISC0_CLR = PMU_MISC0_REFTOP_PWD_MASK;  in bandgap_set()
130 		while ((PMU->MISC0 & PMU_MISC0_REFTOP_VBGUP_MASK) == 0) {  in bandgap_set()
133 		/* Disable low power bandgap */  in bandgap_set()
134 		XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK;  in bandgap_set()
136 		/* Disable bandgap in PMU and switch to low power one */  in bandgap_set()
137 		XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK;  in bandgap_set()
138 		PMU->MISC0_SET = PMU_MISC0_REFTOP_PWD_MASK;  in bandgap_set()
142 /* Should only be used if core clocks have been reduced- drops SOC voltage */
145 	/* Move to the internal RC oscillator, since we are using low power clocks */  in lpm_drop_voltage()
152 	 * low power mode stability, try raising this voltage value.  in lpm_drop_voltage()
158 	/* Disable normal regulators */  in lpm_drop_voltage()
161 	/* Disable analog bandgap */  in lpm_drop_voltage()
173 	/* Disable weak LDOs */  in lpm_raise_voltage()
185 /* Sets device into low power mode */
199 			/* Drop the SOC clocks to low power mode, and decrease core voltage */  in pm_state_set()
215 /* Handle SOC specific activity after Low Power Mode Exit */
242 /* Initialize power system */
248 	/* Ensure clocks to ARM core memory will not be gated in low power mode  in rt10xx_power_init()
251 	CCM->CGPR |= CCM_CGPR_INT_MEM_CLK_LPM_MASK;  in rt10xx_power_init()
258 	IOMUXC_GPR->GPR1 |= IOMUXC_GPR_GPR1_GINT_MASK;  in rt10xx_power_init()
262 	/* Set target voltage for low power mode to 0.925V*/  in rt10xx_power_init()
264 	/* Reconfigure DCDC to disable internal load resistor */  in rt10xx_power_init()
269 	/* Enable high gate drive on power FETs to reduce leakage current */  in rt10xx_power_init()