Lines Matching full:org
33 org = XCHAL_RESET_VECTOR0_PADDR_IRAM, symbol
36 org = XCHAL_RESET_VECTOR0_PADDR_IRAM + MEM_RESET_TEXT_SIZE,
39 org = XCHAL_VECBASE_RESET_PADDR_IRAM,
42 org = XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
45 org = XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM,
48 org = XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
51 org = XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM,
54 org = XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
57 org = XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM,
60 org = XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
63 org = XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM,
66 org = XCHAL_KERNEL_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
69 org = XCHAL_KERNEL_VECTOR_PADDR_IRAM,
72 org = XCHAL_USER_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
75 org = XCHAL_USER_VECTOR_PADDR_IRAM,
78 org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
81 org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM,
84 org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE,
87 org = SDRAM0_BASE,
90 org = SDRAM1_BASE + SOF_MAILBOX_SIZE,
94 org = IDT_BASE,
99 org = UUID_ENTRY_ELF_BASE,
102 org = LOG_ENTRY_ELF_BASE,
105 org = EXT_MANIFEST_ELF_BASE,