18 	/* Move M4 core to the configured RDC domain */  in SOC_RdcInit()
21 	/* Set access to WDOG3 for M4 core */  in SOC_RdcInit()
27 	/* Set access to UART_1 for M4 core */  in SOC_RdcInit()
31 	/* Set access to UART_2 for M4 core */  in SOC_RdcInit()
35 	/* Set access to UART_3 for M4 core */  in SOC_RdcInit()
39 	/* Set access to UART_4 for M4 core */  in SOC_RdcInit()
43 	/* Set access to UART_5 for M4 core */  in SOC_RdcInit()
47 	/* Set access to UART_6 for M4 core */  in SOC_RdcInit()
51 	/* Set access to GPIO_1 for M4 core */  in SOC_RdcInit()
55 	/* Set access to GPIO_2 for M4 core */  in SOC_RdcInit()
59 	/* Set access to GPIO_3 for M4 core */  in SOC_RdcInit()
63 	/* Set access to GPIO_4 for M4 core */  in SOC_RdcInit()
67 	/* Set access to GPIO_5 for M4 core */  in SOC_RdcInit()
71 	/* Set access to GPIO_6 for M4 core */  in SOC_RdcInit()
75 	/* Set access to GPIO_7 for M4 core */  in SOC_RdcInit()
80 	/* Set access to MU B for M4 core */  in SOC_RdcInit()
85 	/* Set access to EPIT_1 for M4 core */  in SOC_RdcInit()
89 	/* Set access to EPIT_2 for M4 core */  in SOC_RdcInit()
94 	/* Set access to I2C-1 for M4 core */  in SOC_RdcInit()
98 	/* Set access to I2C-2 for M4 core */  in SOC_RdcInit()
102 	/* Set access to I2C-3 for M4 core */  in SOC_RdcInit()
106 	/* Set access to I2C-4 for M4 core */  in SOC_RdcInit()
111 	/* Set access to PWM-1 for M4 core */  in SOC_RdcInit()
115 	/* Set access to PWM-2 for M4 core */  in SOC_RdcInit()
119 	/* Set access to PWM-3 for M4 core */  in SOC_RdcInit()
123 	/* Set access to PWM-4 for M4 core */  in SOC_RdcInit()
127 	/* Set access to PWM-5 for M4 core */  in SOC_RdcInit()
131 	/* Set access to PWM-6 for M4 core */  in SOC_RdcInit()
135 	/* Set access to PWM-7 for M4 core */  in SOC_RdcInit()
139 	/* Set access to PWM-8 for M4 core */  in SOC_RdcInit()
143 	/* Set access to ADC-1 for M4 core */  in SOC_RdcInit()
147 	/* Set access to ADC-2 for M4 core */  in SOC_RdcInit()
188 	/* OSC/PLL is already initialized by Cortex-A9 core */  in SOC_ClockInit()