Lines Matching +full:inter +full:- +full:frame
4 * SPDX-License-Identifier: Apache-2.0
20 * must meet the alignment requirement of cortex-m4.
44 __ASSERT(reg == val, "16-bit reg access failed!"); \
50 __ASSERT(reg == val, "32-bit reg access failed!"); \
90 /* 0x102: High-Frequency Reference Divisor I */
92 /* 0x104: High-Frequency Reference Divisor F */
127 /* 0x008 - 0D: Power-Down Control 1 - 6 */
130 /* 0x020 - 21: Power-Down Control 1 - 2 */
133 /* 0x024: Power-Down Control 7 */
137 /* PMC internal inline functions for multi-registers */
143 return 0x024 + ctl_no - 6; in npcx_pwdwn_ctl_offset()
147 /* Macro functions for PMC multi-registers */
223 /* 0x010 - 1F: Device Alternate Function 0 - F */
226 /* 0x026: Low-Voltage GPIO Pins Control 5 */
229 /* 0x028: Pull-Up/Pull-Down Enable 0 */
231 /* 0x029: Pull-Up/Pull-Down Enable 1 */
233 /* 0x02A - 2E: Low-Voltage GPIO Pins Control 0 - 4 */
237 /* Macro functions for SCFG multi-registers */
342 * Universal Asynchronous Receiver-Transmitter (UART) device registers
357 /* 0x008: Frame Select */
420 /* Macro functions for MIWU multi-registers */
439 * General-Purpose I/O (GPIO) device registers
448 /* 0x003: Port GPIOx Pull-Up or Pull-Down Enable */
450 /* 0x004: Port GPIOx Pull-Up/Down Selection */
488 * Analog-To-Digital Converter (ADC) device registers
516 /* ADC internal inline functions for multi-registers */
608 /* 0x010: eSPI Wake-Up Enable */
647 /* 0x100 - 127: Virtual Wire Event Slave-to-Master 0 - 9 */
650 /* 0x140 - 16F: Virtual Wire Event Master-to-Slave 0 - 11 */
653 /* 0x180 - 1BF: Virtual Wire GPIO Event Master-to-Slave 0 - 15 */
658 /* 0x300 - 34F: OOB Receive Buffer 0 - 19 */
661 /* 0x380 - 3CF: OOB Transmit Buffer 0-19 */
666 /* 0x400 - 443: Flash Receive Buffer 0-17 */
669 /* 0x480 - 497: Flash Transmit Buffer 0-16 */
675 /* 0x600 - 63F */
677 /* 0x640 - 67F */
679 /* 0x680 - 6BF */
824 * Mobile System Wake-Up Control (MSWC) device registers
1102 /* 0x008: Core-to-Host Modules Access Enable */
1186 /* 0x012: SMB Tx-FIFO Control */
1196 /* 0x01A: SMB Tx-FIFO Status */
1199 /* 0x01C: SMB Rx-FIFO Status */
1202 /* 0x01E: SMB Rx-FIFO Control */
1276 * Internal 32-bit Timer (ITIM32) device registers
1280 /* 0x001: Internal 32-bit Timer Prescaler */
1283 /* 0x004: Internal 32-bit Timer Control and Status */
1286 /* 0x008: Internal 32-Bit Timer Counter */
1291 * Internal 64-bit Timer (ITIM54) device registers
1295 /* 0x001: Internal 64-bit Timer Prescaler */
1298 /* 0x004: Internal 64-bit Timer Control and Status */
1301 /* 0x008: Internal 32-Bit Timer Counter */
1303 /* 0x00C: Internal 32-Bit Timer Counter */
1351 /* 0x01A: Timer Wake-Up Enable */
1492 /* 0x020: UMA Data Bytes 0-3 */
1510 /* 0x034: UMA address byte 0-3 */
1512 /* 0x038-0x3C */
1516 /* 0x03E-0x3F */
1519 /* 0x034: UMA address byte 0-3 */
1521 /* 0x038-0x3B */
1560 #define UMA_FLD_ADDR BIT(NPCX_UMA_CTS_A_SIZE) /* 3-bytes ADR field */
1561 #define UMA_FLD_NO_CMD BIT(NPCX_UMA_CTS_C_SIZE) /* No 1-Byte CMD field */
1618 /* 0x010 - 0x04F: PECI Data In/Out */
1645 /* 0x005: Keyboard Scan In Pull-Up Enable */
1713 /* 0x011: SHI Configuration 6 - only in chips which support enhanced buffer mode */
1715 /* 0x012: Single Byte Output Buffer - only in chips which support enhanced buffer mode */
1794 /* Software-triggered Pheripheral Reset Controller Register */
1802 /* Improved Inter Integrated Circuit (I3C) device registers */
1822 /* 0x024-0x02B: reserved */
1830 /* 0x038: Target Write Half-Word Data */
1832 /* 0x03C: Target Write Half-Word Data as End */
1838 /* 0x048: Target Read Half-Word Data */
1840 /* 0x04C-0x05B: reserved */
1878 /* 0x0A0-0x0AB: reserved */
1886 /* 0x0B8: Controller Write Half-Word Data */
1888 /* 0x0BC: Controller Write Half-Word Data as End */
1894 /* 0x0C8: Controller Read Half-Word Data */
1896 /* 0x0CC-0x0D7: reserved */
1906 /* 0x0E8-0x0FF reserved */
1914 /* 0x10C-0x113: reserved */