Lines Matching +full:falling +full:- +full:edge

4  * SPDX-License-Identifier: Apache-2.0
24 /* Mode 0: Clock idle = Low. Data change falling edge, sample rising edge */
26 /* Mode 1: Clock idle = Low. Data change rising edge, sample falling edge */
28 /* Mode 2: Clock idle = High. Data change rising edge, sample falling edge */
30 /* Mode 3: Clock idle = High. Data change falling edge, sample rising edge */
140 /* MOSI data changes on first clock edge of clock pulse */
142 /* MOSI data changes on second clock edge of clock pulse */
146 /* MISO data capture on first clock edge of clock pulse */
148 /* MISO data capture on second clock edge of clock pulse */
368 /* Each Local DMA channel implements 4 32-bit registers.
373  * offset 0x0c: reserved read-only 0
380 /* re-enable channel upon done */