Lines Matching full:monitor

284  * Clock monitor 32KHz period counter (Offset +C0h, RO)
285  * Clock monitor 32KHz high counter (Offset +C4h, RO)
286  * Clock monitor 32KHz period counter minimum (Offset +C8h, RW)
287  * Clock monitor 32KHz period counter maximum (Offset +CCh, RW)
288  * Clock monitor 32KHz Duty Cycle variation counter (Offset +D0h, RO)
289  * Clock monitor 32KHz Duty Cycle variation counter maximum (Offset +D4h, RW)
294  * Clock monitor 32KHz Valid Count (Offset +0xD8, RO)
295  * Clock monitor 32KHz Valid Count minimum (Offset +0xDC, RW)
299 /* Clock monitor control register (Offset +0xE0, RW) */
307 /* Clock monitor interrupt status (Offset +0xE4, R/W1C) */
317 /* Clock monitor interrupt enable (Offset +0xE8, RW) */
327 /* PCR 32KHz clock monitor uses 48 MHz for all counters */