Lines Matching refs:SHLU32
38 #define MCHP_GPIO_CTRL_PWRG_VCC_IO SHLU32(1, MCHP_GPIO_CTRL_PWRG_POS)
39 #define MCHP_GPIO_CTRL_PWRG_OFF SHLU32(2, MCHP_GPIO_CTRL_PWRG_POS)
40 #define MCHP_GPIO_CTRL_PWRG_RSVD SHLU32(3, MCHP_GPIO_CTRL_PWRG_POS)
41 #define MCHP_GPIO_CTRL_PWRG_MASK SHLU32(3, MCHP_GPIO_CTRL_PWRG_POS)
47 #define MCHP_GPIO_CTRL_IDET_LVL_HI SHLU32(1, MCHP_GPIO_CTRL_IDET_POS)
48 #define MCHP_GPIO_CTRL_IDET_DISABLE SHLU32(4, MCHP_GPIO_CTRL_IDET_POS)
49 #define MCHP_GPIO_CTRL_IDET_REDGE SHLU32(0xd, MCHP_GPIO_CTRL_IDET_POS)
50 #define MCHP_GPIO_CTRL_IDET_FEDGE SHLU32(0xe, MCHP_GPIO_CTRL_IDET_POS)
51 #define MCHP_GPIO_CTRL_IDET_BEDGE SHLU32(0xf, MCHP_GPIO_CTRL_IDET_POS)
52 #define MCHP_GPIO_CTRL_IDET_MASK SHLU32(0xf, MCHP_GPIO_CTRL_IDET_POS)
83 #define MCHP_GPIO_CTRL_MUX_MASK SHLU32(7, MCHP_GPIO_CTRL_MUX_POS)
86 #define MCHP_GPIO_CTRL_MUX_F1 SHLU32(1, MCHP_GPIO_CTRL_MUX_POS)
87 #define MCHP_GPIO_CTRL_MUX_F2 SHLU32(2, MCHP_GPIO_CTRL_MUX_POS)
88 #define MCHP_GPIO_CTRL_MUX_F3 SHLU32(3, MCHP_GPIO_CTRL_MUX_POS)
89 #define MCHP_GPIO_CTRL_MUX_F4 SHLU32(4, MCHP_GPIO_CTRL_MUX_POS)
90 #define MCHP_GPIO_CTRL_MUX_F5 SHLU32(5, MCHP_GPIO_CTRL_MUX_POS)
91 #define MCHP_GPIO_CTRL_MUX_F6 SHLU32(6, MCHP_GPIO_CTRL_MUX_POS)
92 #define MCHP_GPIO_CTRL_MUX_F7 SHLU32(7, MCHP_GPIO_CTRL_MUX_POS)
93 #define MCHP_GPIO_CTRL_MUX(n) SHLU32(((n) & 0x7u), MCHP_GPIO_CTRL_MUX_POS)