Lines Matching +full:0 +full:x0600
14 #define MCHP_ESPI_IO_PC_OFS 0x0100u
15 #define MCHP_ESPI_IO_HOST_BAR_OFS 0x0120u
16 #define MCHP_ESPI_IO_LTR_OFS 0x0220u
17 #define MCHP_ESPI_IO_OOB_OFS 0x0240u
18 #define MCHP_ESPI_IO_FC_OFS 0x0280u
19 #define MCHP_ESPI_IO_CAP_OFS 0x02b0u
20 #define MCHP_ESPI_IO_SIRQ_OFS 0x03a0u
22 /* eSPI Global Capabilities 0 */
23 #define MCHP_ESPI_GBL_CAP0_MASK 0x0fu
24 #define MCHP_ESPI_GBL_CAP0_PC_SUPP BIT(0)
30 #define MCHP_ESPI_GBL_CAP1_MASK 0xffu
31 #define MCHP_ESPI_GBL_CAP1_MAX_FREQ_POS 0u
32 #define MCHP_ESPI_GBL_CAP1_MAX_FREQ_MASK 0x07u
33 #define MCHP_ESPI_GBL_CAP1_MAX_FREQ_20M 0x00u
34 #define MCHP_ESPI_GBL_CAP1_MAX_FREQ_25M 0x01u
35 #define MCHP_ESPI_GBL_CAP1_MAX_FREQ_33M 0x02u
36 #define MCHP_ESPI_GBL_CAP1_MAX_FREQ_50M 0x03u
37 #define MCHP_ESPI_GBL_CAP1_MAX_FREQ_66M 0x04u
41 #define MCHP_ESPI_GBL_CAP1_ALERT_ON_IO1 0u
43 #define MCHP_ESPI_GBL_CAP1_IO_MODE_MASK0 0x03u
44 #define MCHP_ESPI_GBL_CAP1_IO_MODE_MASK SHLU32(0x03u, 4)
45 #define MCHP_ESPI_GBL_CAP1_IO_MODE0_1 0u
79 #define MCHP_ESPI_PC_CAP_MASK 0x07u
80 #define MCHP_ESPI_PC_CAP_MAX_PLD_SZ_MASK 0x07u
81 #define MCHP_ESPI_PC_CAP_MAX_PLD_SZ_64 0x01u
82 #define MCHP_ESPI_PC_CAP_MAX_PLD_SZ_128 0x02u
83 #define MCHP_ESPI_PC_CAP_MAX_PLD_SZ_256 0x03u
86 #define MCHP_ESPI_VW_CAP_MASK 0x3fu
87 #define MCHP_ESPI_VW_CAP_MAX_VW_CNT_MASK 0x3fu
90 #define MCHP_ESPI_OOB_CAP_MASK 0x07u
91 #define MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_MASK 0x07u
92 #define MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_73 0x01u
93 #define MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_137 0x02u
94 #define MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_265 0x03u
97 #define MCHP_ESPI_FC_CAP_MASK 0xffu
98 #define MCHP_ESPI_FC_CAP_MAX_PLD_SZ_MASK 0x07u
99 #define MCHP_ESPI_FC_CAP_MAX_PLD_SZ_64 0x01u
101 #define MCHP_ESPI_FC_CAP_SHARE_MASK0 0x03u
105 #define MCHP_ESPI_FC_CAP_SHARE_MAF_ONLY 0u
116 #define MCHP_ESPI_FC_CAP_MAX_RD_SZ_MASK0 0x07u
125 #define MCHP_ESPI_PC_READY_MASK 0x01u;
126 #define MCHP_ESPI_PC_READY 0x01u;
129 #define MCHP_ESPI_OOB_READY_MASK 0x01u;
130 #define MCHP_ESPI_OOB_READY 0x01u;
133 #define MCHP_ESPI_FC_READY_MASK 0x01u;
134 #define MCHP_ESPI_FC_READY 0x01u;
137 #define MCHP_ESPI_RST_ISTS_MASK 0x03u;
138 #define MCHP_ESPI_RST_ISTS_POS 0u
144 #define MCHP_ESPI_RST_IEN_MASK 0x01u
145 #define MCHP_ESPI_RST_IEN 0x01u
148 #define MCHP_ESPI_PLTRST_SRC_MASK 0x01u
149 #define MCHP_ESPI_PLTRST_SRC_POS 0u
150 #define MCHP_ESPI_PLTRST_SRC_IS_PIN 0x01u
151 #define MCHP_ESPI_PLTRST_SRC_IS_VW 0x00u
154 #define MCHP_ESPI_VW_READY_MASK 0x01u
155 #define MCHP_ESPI_VW_READY 0x01u
158 #define MCHP_ESPI_SERASE_SZ_1K_BITPOS 0
166 #define MCHP_ESPI_SERASE_SZ_1K BIT(0)
177 #define MCHP_ESPI_VW_ERR_STS_MASK 0x33u
178 #define MCHP_ESPI_VW_ERR_STS_FATAL_POS 0u
195 #define MCHP_ESPI_VW_EN_STS_MASK 0x01u
196 #define MCHP_ESPI_VW_EN_STS_RO 0x01u
199 * MCHP_ESPI_IO_PC - eSPI IO Peripheral Channel registers @ 0x400F3500
203 #define MCHP_ESPI_PC_LC_LEN_POS 0u
204 #define MCHP_ESPI_PC_LC_LEN_MASK0 0x0fffu
205 #define MCHP_ESPI_PC_LC_LEN_MASK 0x0fffu
207 #define MCHP_ESPI_PC_LC_TYPE_MASK0 0xffu
208 #define MCHP_ESPI_PC_LC_TYPE_MASK (0xffu << 12)
210 #define MCHP_ESPI_PC_LC_TAG_MASK0 0x0fu
211 #define MCHP_ESPI_PC_LC_TAG_MASK (0x0fu << 20)
231 * PC_LC_ADDR_LSW (@ 0x0000) Periph Chan Last Cycle address LSW
232 * PC_LC_ADDR_MSW (@ 0x0004) Periph Chan Last Cycle address MSW
233 * PC_LC_LEN_TYPE_TAG (@ 0x0008) Periph Chan Last Cycle length/type/tag
234 * PC_ERR_ADDR_LSW (@ 0x000C) Periph Chan Error Address LSW
235 * PC_ERR_ADDR_MSW (@ 0x0010) Periph Chan Error Address MSW
236 * PC_STATUS (@ 0x0014) Periph Chan Status
237 * PC_IEN (@ 0x0018) Periph Chan IEN
247 #define MCHP_ESPI_LTR_STS_TX_DONE_POS 0u /* RW1C */
256 #define MCHP_ESPI_LTR_IEN_TX_DONE_POS 0u
259 #define MCHP_ESPI_LTR_CTRL_START_POS 0u
262 #define MCHP_ESPI_LTR_CTRL_TAG_MASK0 0x0fu
266 #define MCHP_ESPI_LTR_MSG_VAL_POS 0u
267 #define MCHP_ESPI_LTR_MSG_VAL_MASK0 0x3ffu
271 #define MCHP_ESPI_LTR_MSG_SC_MASK0 0x07u
275 #define MCHP_ESPI_LTR_MSG_RT_MASK0 0x03u
279 #define MCHP_ESPI_LTR_MSG_RT_VAL 0u
282 #define MCHP_ESPI_LTR_MSG_REQ_INF 0u
287 #define MCHP_ESPI_OOB_RX_ADDR_LSW_MASK 0xfffffffcu
288 #define MCHP_ESPI_OOB_TX_ADDR_LSW_MASK 0xfffffffcu
292 #define MCHP_ESPI_OOB_RX_LEN_POS 0u
293 #define MCHP_ESPI_OOB_RX_LEN_MASK 0x1fffu
296 #define MCHP_ESPI_OOB_RX_BUF_LEN_MASK0 0x1fffu
301 #define MCHP_ESPI_OOB_TX_MSG_LEN_POS 0u
302 #define MCHP_ESPI_OOB_TX_MSG_LEN_MASK 0x1fffu
306 #define MCHP_ESPI_OOB_RX_CTRL_AVAIL_POS 0u /* WO */
312 #define MCHP_ESPI_OOB_RX_CTRL_MAX_SZ_MASK0 0x07u
318 #define MCHP_ESPI_OOB_RX_IEN_POS 0u
322 #define MCHP_ESPI_OOB_RX_STS_DONE_POS 0u /* RW1C */
331 #define MCHP_ESPI_OOB_RX_STS_TAG_MASK0 0x0fu
335 #define MCHP_ESPI_OOB_RX_STS_ALL_RW1C 0x07u
336 #define MCHP_ESPI_OOB_RX_STS_ALL 0x0fu
339 #define MCHP_ESPI_OOB_TX_CTRL_START_POS 0u /* WO */
342 #define MCHP_ESPI_OOB_TX_CTRL_TAG_MASK0 0x0fu
347 #define MCHP_ESPI_OOB_TX_IEN_DONE_POS 0u
351 #define MCHP_ESPI_OOB_TX_IEN_ALL 0x03u
354 #define MCHP_ESPI_OOB_TX_STS_DONE_POS 0u /* RW1C */
370 #define MCHP_ESPI_OOB_TX_STS_ALL_RW1C 0x2fu
374 #define MCHP_ESPI_FC_MEM_ADDR_LSW_MASK 0xfffffffcu
377 #define MCHP_ESPI_FC_CTRL_START_POS 0u /* WO */
380 #define MCHP_ESPI_FC_CTRL_FUNC_MASK0 0x03u
383 #define MCHP_ESPI_FC_CTRL_RD0 0x00u
384 #define MCHP_ESPI_FC_CTRL_WR0 0x01u
385 #define MCHP_ESPI_FC_CTRL_ERS0 0x02u
386 #define MCHP_ESPI_FC_CTRL_ERL0 0x03u
392 #define MCHP_ESPI_FC_CTRL_TAG_MASK0 0x0fu
403 #define MCHP_ESPI_FC_IEN_DONE_POS 0u
409 #define MCHP_ESPI_FC_CFG_BUSY_POS 0u /* RO */
412 #define MCHP_ESPI_FC_CFG_ERBSZ_MASK0 0x07u
416 SHLU32(0x01u, MCHP_ESPI_FC_CFG_ERBSZ_POS)
418 SHLU32(0x02u, MCHP_ESPI_FC_CFG_ERBSZ_POS)
420 SHLU32(0x03u, MCHP_ESPI_FC_CFG_ERBSZ_POS)
422 SHLU32(0x04u, MCHP_ESPI_FC_CFG_ERBSZ_POS)
424 SHLU32(0x05u, MCHP_ESPI_FC_CFG_ERBSZ_POS)
426 #define MCHP_ESPI_FC_CFG_MAXPLD_MASK0 0x07u
430 SHLU32(0x01u, MCHP_ESPI_FC_CFG_MAXPLD_POS)
432 SHLU32(0x02u, MCHP_ESPI_FC_CFG_MAXPLD_POS)
434 SHLU32(0x03u, MCHP_ESPI_FC_CFG_MAXPLD_POS)
438 #define MCHP_ESPI_FC_CFG_MAXRD_MASK0 0x07u
442 SHLU32(0x01u, MCHP_ESPI_FC_CFG_MAXRD_POS)
444 SHLU32(0x02u, MCHP_ESPI_FC_CFG_MAXRD_POS)
446 SHLU32(0x03u, MCHP_ESPI_FC_CFG_MAXRD_POS)
448 SHLU32(0x04u, MCHP_ESPI_FC_CFG_MAXRD_POS)
450 SHLU32(0x05u, MCHP_ESPI_FC_CFG_MAXRD_POS)
452 SHLU32(0x06u, MCHP_ESPI_FC_CFG_MAXRD_POS)
454 SHLU32(0x07u, MCHP_ESPI_FC_CFG_MAXRD_POS)
456 #define MCHP_ESPI_FC_CFG_FORCE_MS_MASK0 0x03u
460 #define MCHP_ESPI_FC_CFG_FORCE_NONE 0u
463 SHLU32(0x02u, MCHP_ESPI_FC_CFG_FORCE_MS_POS)
466 SHLU32(0x03u, MCHP_ESPI_FC_CFG_FORCE_MS_POS)
469 #define MCHP_ESPI_FC_STS_CHAN_EN_POS 0u /* RO */
494 #define MCHP_ESPI_FC_STS_ALL_RW1C 0x0bfeu
503 #define MCHP_ESPI_IOBAR_LDN_MBOX 0u
528 * configuration registers. (Defaults to 0x2E/0x2F)
530 #define MCHP_ESPI_IOBAR_INIT_DFLT 0x2eu
533 * EC_IRQ: A write to bit[0] triggers EC SERIRQ. The actual
536 #define MCHP_ESPI_EC_IRQ_GEN (1u << 0)
539 #define MCHP_ESPI_IO_BAR_HOST_VALID_POS 0u
543 #define MCHP_ESPI_IO_BAR_HOST_ADDR_MASK0 0xffffu
544 #define MCHP_ESPI_IO_BAR_HOST_ADDR_MASK 0xffff0000u
547 #define MCHP_ESPI_SIRQ_MBOX_SIRQ 0u
573 * Values 0x00u through 0x7Fu are sent using VWire host index 0x00
574 * Values 0x80h through 0xFEh are sent using VWire host index 0x01
575 * All registers reset default is 0xFFu (disabled).
577 #define MCHP_ESPI_IO_SIRQ_DIS 0xFFu
581 #define MCHP_ESPI_BM_STS_DONE_1_POS 0u /* RW1C */
626 #define MCHP_ESPI_BM_STS_ALL_RW1C_1 0x0bfdu
627 #define MCHP_ESPI_BM_STS_ALL_RW1C_2 0x0bfd0000u
630 #define MCHP_ESPI_BM1_IEN_DONE_POS 0u
636 #define MCHP_ESPI_BM1_CFG_TAG_POS 0u
637 #define MCHP_ESPI_BM1_CFG_TAG_MASK0 0x0fu
638 #define MCHP_ESPI_BM1_CFG_TAG_MASK 0x0fu
640 #define MCHP_ESPI_BM2_CFG_TAG_MASK0 0x0fu
641 #define MCHP_ESPI_BM2_CFG_TAG_MASK 0x0f0000u
644 #define MCHP_ESPI_BM1_CTRL_START_POS 0u /* WO */
653 #define MCHP_ESPI_BM1_CTRL_CTYPE_MASK0 0x03u
656 #define MCHP_ESPI_BM1_CTRL_CTYPE_RD_ADDR32 0x00u
658 SHLU32(0x01u, MCHP_ESPI_BM1_CTRL_CTYPE_POS)
660 SHLU32(0x02u, MCHP_ESPI_BM1_CTRL_CTYPE_POS)
662 SHLU32(0x03u, MCHP_ESPI_BM1_CTRL_CTYPE_POS)
664 #define MCHP_ESPI_BM1_CTRL_LEN_MASK0 0x1fffu
665 #define MCHP_ESPI_BM1_CTRL_LEN_MASK 0x1fff0000u
668 #define MCHP_ESPI_BM1_EC_ADDR_LSW_MASK 0xfffffffcu
671 #define MCHP_ESPI_BM2_CTRL_START_POS 0u /* WO */
680 #define MCHP_ESPI_BM2_CTRL_CTYPE_MASK0 0x03u
681 #define MCHP_ESPI_BM2_CTRL_CTYPE_MASK 0x0300u
682 #define MCHP_ESPI_BM2_CTRL_CTYPE_RD_ADDR32 0x00u
683 #define MCHP_ESPI_BM2_CTRL_CTYPE_WR_ADDR32 0x0100u
684 #define MCHP_ESPI_BM2_CTRL_CTYPE_RD_ADDR64 0x0200u
685 #define MCHP_ESPI_BM2_CTRL_CTYPE_WR_ADDR64 0x0300u
687 #define MCHP_ESPI_BM2_CTRL_LEN_MASK0 0x1fffu
688 #define MCHP_ESPI_BM2_CTRL_LEN_MASK 0x1fff0000u
691 #define MCHP_ESPI_BM2_EC_ADDR_LSW_MASK 0xfffffffcu
694 * MCHP_ESPI_MEM_BAR_EC @ 0x400F3930
696 * Memory BAR memory address mask bits in bits[7:0]
699 #define MCHP_ESPI_EBAR_H0_MEM_MASK_POS 0u
700 #define MCHP_ESPI_EBAR_H0_MEM_MASK_MASK 0xffu
702 #define MCHP_ESPI_EBAR_H0_LDN_MASK0 0x3fu
703 #define MCHP_ESPI_EBAR_H0_LDN_MASK 0x3f00u
706 * MCHP_ESPI_MEM_BAR_HOST @ 0x400F3B30
708 * bit[0] (RW) = Valid bit
709 * bits[15:1] = Reserved, read-only 0
710 * bits[47:16] (RW) = bits[31:0] of the Host Memory address.
714 #define MCHP_ESPI_HBAR_VALID_POS 0u
715 #define MCHP_ESPI_HBAR_VALID_MASK 0x01u
719 * only implement bits[47:0]
721 #define MCHP_ESPI_HBAR_VALID_OFS 0x00u /* byte 0 */
723 #define MCHP_ESPI_HBAR_ADDR_B0_OFS 0x02u /* byte 2 */
724 #define MCHP_ESPI_HBAR_ADDR_B1_OFS 0x03u /* byte 3 */
725 #define MCHP_ESPI_HBAR_ADDR_B2_OFS 0x04u /* byte 4 */
726 #define MCHP_ESPI_HBAR_ADDR_B3_OFS 0x05u /* byte 5 */
728 #define MCHP_EC_SRAM_BAR_H0_VALID_POS 0u
729 #define MCHP_EC_SRAM_BAR_H0_VALID_MASK0 0x01u
730 #define MCHP_EC_SRAM_BAR_H0_VALID_MASK 0x01u
731 #define MCHP_EC_SRAM_BAR_H0_VALID 0x01u
733 #define MCHP_EC_SRAM_BAR_H0_ACCESS_MASK0 0x03u
734 #define MCHP_EC_SRAM_BAR_H0_ACCESS_MASK 0x06u
735 #define MCHP_EC_SRAM_BAR_H0_ACCESS_NONE 0x00u
736 #define MCHP_EC_SRAM_BAR_H0_ACCESS_RO 0x02u
737 #define MCHP_EC_SRAM_BAR_H0_ACCESS_WO 0x04u
738 #define MCHP_EC_SRAM_BAR_H0_ACCESS_RW 0x06u
740 #define MCHP_EC_SRAM_BAR_H0_SIZE_MASK0 0x0fu
741 #define MCHP_EC_SRAM_BAR_H0_SIZE_MASK 0xf0u
742 #define MCHP_EC_SRAM_BAR_H0_SIZE_1B 0x00u
743 #define MCHP_EC_SRAM_BAR_H0_SIZE_2B 0x10u
744 #define MCHP_EC_SRAM_BAR_H0_SIZE_4B 0x20u
745 #define MCHP_EC_SRAM_BAR_H0_SIZE_8B 0x30u
746 #define MCHP_EC_SRAM_BAR_H0_SIZE_16B 0x40u
747 #define MCHP_EC_SRAM_BAR_H0_SIZE_32B 0x50u
748 #define MCHP_EC_SRAM_BAR_H0_SIZE_64B 0x60u
749 #define MCHP_EC_SRAM_BAR_H0_SIZE_128B 0x70u
750 #define MCHP_EC_SRAM_BAR_H0_SIZE_256B 0x80u
751 #define MCHP_EC_SRAM_BAR_H0_SIZE_512B 0x90u
752 #define MCHP_EC_SRAM_BAR_H0_SIZE_1KB 0xa0u
753 #define MCHP_EC_SRAM_BAR_H0_SIZE_2KB 0xb0u
754 #define MCHP_EC_SRAM_BAR_H0_SIZE_4KB 0xc0u
755 #define MCHP_EC_SRAM_BAR_H0_SIZE_8KB 0xd0u
756 #define MCHP_EC_SRAM_BAR_H0_SIZE_16KB 0xe0u
757 #define MCHP_EC_SRAM_BAR_H0_SIZE_32KB 0xf0u
769 IOB_IOC = 0,
797 SIRQ_MBOX = 0, SIRQ_MBOX_SMI, SIRQ_KBC_KIRQ,
807 MEMB_MBOX = 0,
824 }; /* Size = 10 (0xa) */
831 }; /* Size = 10 (0xa) */
838 }; /* Size = 10 (0xa) */
845 }; /* Size = 10 (0xa) */
848 struct espi_iom_regs { /* @ 0x400F3400 */
849 volatile uint8_t RTIDX; /* @ 0x0000 */
850 volatile uint8_t RTDAT; /* @ 0x0001 */
853 volatile uint32_t PCLC[3]; /* @ 0x0100 */
854 volatile uint32_t PCERR[2]; /* @ 0x010C */
855 volatile uint32_t PCSTS; /* @ 0x0114 */
856 volatile uint32_t PCIEN; /* @ 0x0118 */
858 volatile uint32_t PCBINH[2]; /* @ 0x0120 */
859 volatile uint32_t PCBINIT; /* @ 0x0128 */
860 volatile uint32_t PCECIRQ; /* @ 0x012C */
861 volatile uint32_t PCCKNP; /* @ 0x0130 */
862 volatile uint32_t PCBARI[29]; /* @ 0x0134 */
864 volatile uint32_t PCLTRSTS; /* @ 0x0220 */
865 volatile uint32_t PCLTREN; /* @ 0x0224 */
866 volatile uint32_t PCLTRCTL; /* @ 0x0228 */
867 volatile uint32_t PCLTRM; /* @ 0x022C */
869 volatile uint32_t OOBRXA[2]; /* @ 0x0240 */
870 volatile uint32_t OOBTXA[2]; /* @ 0x0248 */
871 volatile uint32_t OOBRXL; /* @ 0x0250 */
872 volatile uint32_t OOBTXL; /* @ 0x0254 */
873 volatile uint32_t OOBRXC; /* @ 0x0258 */
874 volatile uint32_t OOBRXIEN; /* @ 0x025C */
875 volatile uint32_t OOBRXSTS; /* @ 0x0260 */
876 volatile uint32_t OOBTXC; /* @ 0x0264 */
877 volatile uint32_t OOBTXIEN; /* @ 0x0268 */
878 volatile uint32_t OOBTXSTS; /* @ 0x026C */
880 volatile uint32_t FCFA[2]; /* @ 0x0280 */
881 volatile uint32_t FCBA[2]; /* @ 0x0288 */
882 volatile uint32_t FCLEN; /* @ 0x0290 */
883 volatile uint32_t FCCTL; /* @ 0x0294 */
884 volatile uint32_t FCIEN; /* @ 0x0298 */
885 volatile uint32_t FCCFG; /* @ 0x029C */
886 volatile uint32_t FCSTS; /* @ 0x02A0 */
888 volatile uint32_t VWSTS; /* @ 0x02B0 */
890 volatile uint8_t CAPID; /* @ 0x02E0 */
891 volatile uint8_t CAP0; /* @ 0x02E1 */
892 volatile uint8_t CAP1; /* @ 0x02E2 */
893 volatile uint8_t CAPPC; /* @ 0x02E3 */
894 volatile uint8_t CAPVW; /* @ 0x02E4 */
895 volatile uint8_t CAPOOB; /* @ 0x02E5 */
896 volatile uint8_t CAPFC; /* @ 0x02E6 */
897 volatile uint8_t PCRDY; /* @ 0x02E7 */
898 volatile uint8_t OOBRDY; /* @ 0x02E8 */
899 volatile uint8_t FCRDY; /* @ 0x02E9 */
900 volatile uint8_t ERIS; /* @ 0x02EA */
901 volatile uint8_t ERIE; /* @ 0x02EB */
902 volatile uint8_t PLTSRC; /* @ 0x02EC */
903 volatile uint8_t VWRDY; /* @ 0x02ED */
904 volatile uint8_t SAFEBS; /* @ 0x02EE */
907 volatile uint32_t ACTV; /* @ 0x0330 */
908 volatile uint32_t IOHBAR[29]; /* @ 0x0334 */
910 volatile uint8_t SIRQ[19]; /* @ 0x03ac */
913 volatile uint32_t VWERREN; /* @ 0x03f0 */
915 struct espi_io_mbar MBAR[10]; /* @ 0x0530 */
917 struct espi_sram_bar SRAMBAR[2]; /* @ 0x05AC */
919 volatile uint32_t BM_STATUS; /* @ 0x0600 */
920 volatile uint32_t BM_IEN; /* @ 0x0604 */
921 volatile uint32_t BM_CONFIG; /* @ 0x0608 */
923 volatile uint32_t BM_CTRL1; /* @ 0x0610 */
924 volatile uint32_t BM_HADDR1_LSW; /* @ 0x0614 */
925 volatile uint32_t BM_HADDR1_MSW; /* @ 0x0618 */
926 volatile uint32_t BM_EC_ADDR1_LSW; /* @ 0x061C */
927 volatile uint32_t BM_EC_ADDR1_MSW; /* @ 0x0620 */
928 volatile uint32_t BM_CTRL2; /* @ 0x0624 */
929 volatile uint32_t BM_HADDR2_LSW; /* @ 0x0628 */
930 volatile uint32_t BM_HADDR2_MSW; /* @ 0x062C */
931 volatile uint32_t BM_EC_ADDR2_LSW; /* @ 0x0630 */
932 volatile uint32_t BM_EC_ADDR2_MSW; /* @ 0x0634 */
934 struct espi_mbar_host HMBAR[10]; /* @ 0x0730 */
936 struct espi_sram_host_bar HSRAMBAR[2]; /* @ 0x07AC */
937 }; /* Size = 1984 (0x7c0) */