5  * SPDX-License-Identifier: Apache-2.0
53 		sys_write32(pcr->CLK_REQ[i], vbm_addr);  in soc_debug_sleep_clk_req()
57 	sys_write32(pcr->SYS_SLP_CTRL, vbm_addr);  in soc_debug_sleep_clk_req()
59 	sys_write32(ecs->SLP_STS_MIRROR, vbm_addr);  in soc_debug_sleep_clk_req()
77 	regs->GIRQ22.SRC = UINT32_MAX;  in soc_deep_sleep_non_wake_en()
78 	regs->GIRQ22.EN_SET = MCHP_ESPI_WK_CLK_GIRQ_BIT;  in soc_deep_sleep_non_wake_en()
87 	regs->GIRQ22.EN_CLR = UINT32_MAX;  in soc_deep_sleep_non_wake_dis()
88 	regs->GIRQ22.SRC = UINT32_MAX;  in soc_deep_sleep_non_wake_dis()
92 /* When MEC172x drivers are power-aware this should be move there */
100 	regs->GIRQ21.SRC = MCHP_KEYSCAN_GIRQ_BIT;  in soc_deep_sleep_wake_en()
101 	regs->GIRQ21.EN_SET = MCHP_KEYSCAN_GIRQ_BIT;  in soc_deep_sleep_wake_en()
105 	regs->GIRQ21.SRC = MCHP_PS2_0_PORT0B_WK_GIRQ_BIT;  in soc_deep_sleep_wake_en()
106 	regs->GIRQ21.EN_SET = MCHP_PS2_0_PORT0B_WK_GIRQ_BIT;  in soc_deep_sleep_wake_en()
117 	regs->GIRQ21.EN_CLR = MCHP_PS2_0_PORT0B_WK_GIRQ_BIT;  in soc_deep_sleep_wake_dis()
118 	regs->GIRQ21.SRC = MCHP_PS2_0_PORT0B_WK_GIRQ_BIT;  in soc_deep_sleep_wake_dis()
159 	ds_ctx.ecs[0] = regs->ETM_CTRL;  in deep_sleep_save_ecs()
160 	ds_ctx.ecs[1] = regs->DEBUG_CTRL;  in deep_sleep_save_ecs()
162 	regs->ETM_CTRL = 0;  in deep_sleep_save_ecs()
163 	regs->DEBUG_CTRL = 0x00;  in deep_sleep_save_ecs()
172 	ds_ctx.uart_info[0] = regs->ACTV;  in deep_sleep_save_uarts()
174 		while ((regs->LSR & MCHP_UART_LSR_TEMT) == 0) {  in deep_sleep_save_uarts()
177 	regs->ACTV = 0;  in deep_sleep_save_uarts()
180 	ds_ctx.uart_info[1] = regs->ACTV;  in deep_sleep_save_uarts()
182 		while ((regs->LSR & MCHP_UART_LSR_TEMT) == 0) {  in deep_sleep_save_uarts()
185 	regs->ACTV = 0;  in deep_sleep_save_uarts()
196 		ds_ctx.timers[i] = sys_read32(p->addr);  in deep_sleep_save_timers()
197 		if (p->stop_mask) {  in deep_sleep_save_timers()
198 			sys_write32(ds_ctx.timers[i] | p->stop_mask, p->addr);  in deep_sleep_save_timers()
200 			sys_write32(0, p->addr);  in deep_sleep_save_timers()
211 	regs->ETM_CTRL = ds_ctx.ecs[0];  in deep_sleep_restore_ecs()
212 	regs->DEBUG_CTRL = ds_ctx.ecs[1];  in deep_sleep_restore_ecs()
222 	regs0->ACTV = ds_ctx.uart_info[0];  in deep_sleep_restore_uarts()
223 	regs1->ACTV = ds_ctx.uart_info[1];  in deep_sleep_restore_uarts()
234 		if (p->stop_mask) {  in deep_sleep_restore_timers()
235 			temp = sys_read32(p->addr) & ~(p->stop_mask);  in deep_sleep_restore_timers()
236 			sys_write32(temp, p->addr);  in deep_sleep_restore_timers()
238 			sys_write32(ds_ctx.timers[i] & ~p->restore_mask,  in deep_sleep_restore_timers()
239 				    p->addr);  in deep_sleep_restore_timers()
255 	adc0->CONTROL &= ~(MCHP_ADC_CTRL_ACTV);  in deep_sleep_save_blocks()
261 	ds_ctx.peci_info.peci_ctrl = peci->CONTROL;  in deep_sleep_save_blocks()
262 	ds_ctx.peci_info.peci_dis = ecs->PECI_DIS;  in deep_sleep_save_blocks()
263 	ecs->PECI_DIS |= MCHP_ECS_PECI_DISABLE;  in deep_sleep_save_blocks()
278 	if (ecs->CMP_CTRL & BIT(0)) {  in deep_sleep_save_blocks()
280 		ecs->CMP_CTRL &= ~(MCHP_ECS_ACC_EN0);  in deep_sleep_save_blocks()
286 	/* This low-speed clock derived from the 48MHz clock domain is used as  in deep_sleep_save_blocks()
287 	 * a time base for PWMs and TACHs  in deep_sleep_save_blocks()
290 	ds_ctx.slwclk_info = pcr->SLOW_CLK_CTRL;  in deep_sleep_save_blocks()
291 	pcr->SLOW_CLK_CTRL &= (~MCHP_PCR_SLOW_CLK_CTRL_100KHZ &  in deep_sleep_save_blocks()
296 	if (tfdp->CTRL & MCHP_TFDP_CTRL_EN) {  in deep_sleep_save_blocks()
298 		tfdp->CTRL &= ~MCHP_TFDP_CTRL_EN;  in deep_sleep_save_blocks()
302 	 * include a timer so it should de-assert its CLK_REQ in response  in deep_sleep_save_blocks()
303 	 * to SLP_EN 0->1.  in deep_sleep_save_blocks()
314 	adc0->CONTROL |= MCHP_ADC_CTRL_ACTV;  in deep_sleep_restore_blocks()
320 	ecs->PECI_DIS = ds_ctx.peci_info.peci_dis;  in deep_sleep_restore_blocks()
321 	peci->CONTROL = ds_ctx.peci_info.peci_ctrl;  in deep_sleep_restore_blocks()
334 		ecs->CMP_CTRL |= MCHP_ECS_ACC_EN0;  in deep_sleep_restore_blocks()
341 	pcr->SLOW_CLK_CTRL = ds_ctx.slwclk_info;  in deep_sleep_restore_blocks()
346 		tfdp->CTRL |= MCHP_TFDP_CTRL_EN;  in deep_sleep_restore_blocks()