5  * SPDX-License-Identifier: Apache-2.0
41 	SCB->SCR &= ~(1ul << 2);  in soc_lite_sleep_enable()
42 	PCR_REGS->SYS_SLP_CTRL = MCHP_PCR_SYS_SLP_LIGHT;  in soc_lite_sleep_enable()
46  * Deep sleep: PLL is turned off. Wake is fast. PLL requires
52 	SCB->SCR = (1ul << 2); /* Cortex-M4 SLEEPDEEP */  in soc_deep_sleep_enable()
53 	PCR_REGS->SYS_SLP_CTRL = MCHP_PCR_SYS_SLP_HEAVY;  in soc_deep_sleep_enable()
57  * Clear PCR Sleep control sleep all causing HW to de-assert all peripheral
60  * peripheral state therefore we force HW to de-assert the SLP_EN signals.
64 	PCR_REGS->SYS_SLP_CTRL = 0U;  in soc_deep_sleep_disable()
65 	SCB->SCR &= ~(1ul << 2); /* disable Cortex-M4 SLEEPDEEP */  in soc_deep_sleep_disable()
76 		clkreq = PCR_REGS->CLK_REQ0 | PCR_REGS->CLK_REQ1  in soc_deep_sleep_wait_clk_idle()
77 			 | PCR_REGS->CLK_REQ2 | PCR_REGS->CLK_REQ3  in soc_deep_sleep_wait_clk_idle()
78 			 | PCR_REGS->CLK_REQ4;  in soc_deep_sleep_wait_clk_idle()
79 	} while ((clkreq != (1ul << MCHP_PCR1_CPU_POS)) && (cnt-- != 0));  in soc_deep_sleep_wait_clk_idle()
87  * will be turned back off. For example, if the eSPI master requests eSPI
90  * the request and then turn the PLL back off.  The SMBus and I2C peripherals
96 	GIRQ22_REGS->SRC = 0xfffffffful;  in soc_deep_sleep_non_wake_en()
97 	GIRQ22_REGS->EN_SET = (1ul << 9);  in soc_deep_sleep_non_wake_en()
104 	GIRQ22_REGS->EN_CLR = 0xfffffffful;  in soc_deep_sleep_non_wake_dis()
105 	GIRQ22_REGS->SRC = 0xfffffffful;  in soc_deep_sleep_non_wake_dis()
116 	ecs[0] = ECS_REGS->ETM_CTRL;  in deep_sleep_save_ecs()
117 	ECS_REGS->ETM_CTRL = 0;  in deep_sleep_save_ecs()
127 		(uintptr_t)&B16TMR0_REGS->CTRL, 0
130 		(uintptr_t)&B16TMR1_REGS->CTRL, 0
133 		(uintptr_t)&B32TMR0_REGS->CTRL, 0
136 		(uintptr_t)&B32TMR1_REGS->CTRL, 0
139 		(uintptr_t)&CCT_REGS->CTRL,
152 	uart_activate[0] = UART0_REGS->ACTV;  in deep_sleep_save_uarts()
154 		while ((UART0_REGS->LSR & MCHP_UART_LSR_TEMT) == 0) {  in deep_sleep_save_uarts()
157 	UART0_REGS->ACTV = 0;  in deep_sleep_save_uarts()
158 	uart_activate[1] = UART1_REGS->ACTV;  in deep_sleep_save_uarts()
160 		while ((UART1_REGS->LSR & MCHP_UART_LSR_TEMT) == 0) {  in deep_sleep_save_uarts()
163 	UART1_REGS->ACTV = 0;  in deep_sleep_save_uarts()
164 	uart_activate[2] = UART2_REGS->ACTV;  in deep_sleep_save_uarts()
166 		while ((UART2_REGS->LSR & MCHP_UART_LSR_TEMT) == 0) {  in deep_sleep_save_uarts()
169 	UART2_REGS->ACTV = 0;  in deep_sleep_save_uarts()
179 		timers[i] = REG32(p->addr);  in deep_sleep_save_timers()
180 		REG32(p->addr) = 0;  in deep_sleep_save_timers()
187 	ECS_REGS->ETM_CTRL = ecs[0];  in deep_sleep_restore_ecs()
192 	UART0_REGS->ACTV = uart_activate[0];  in deep_sleep_restore_uarts()
193 	UART1_REGS->ACTV = uart_activate[1];  in deep_sleep_restore_uarts()
194 	UART2_REGS->ACTV = uart_activate[2];  in deep_sleep_restore_uarts()
204 		REG32(p->addr) = timers[i] & ~p->restore_mask;  in deep_sleep_restore_timers()