Lines Matching +full:0 +full:x2e

15  * b[7:0] = Revision
20  * register space at 0x2E/0x2F (default).
23 #define MCHP_GCFG_DEV_ID_REG_MASK	GENMASK(31, 0)
24 #define MCHP_GCFG_REV_ID_POS		0
25 #define MCHP_GCFG_DID_REV_MASK		GENMASK(7, 0)
31 /* Byte[0] at offset 0x1c is the 8-bit revision ID */
36  * Byte[1] at offset 0x1D is the 8-bit Sub-ID
37  * bits[3:0] = package type
40 #define MCHP_GCFG_SUB_ID_OFS		0x1du
41 #define MCHP_GCFG_SUB_ID_PKG_POS	0
42 #define MCHP_GCFG_SUB_ID_PKG_MASK	GENMASK(3, 0)
43 #define MCHP_GCFG_SUB_ID_PKG_UNDEF	0u
52 #define MCHP_GCFG_SUB_ID_FAM_UNDEF	0u
53 #define MCHP_GCFG_SUB_ID_FAM_1		0x10u
54 #define MCHP_GCFG_SUB_ID_FAM_2		0x20u
55 #define MCHP_GCFG_SUB_ID_FAM_3		0x30u
56 #define MCHP_GCFG_SUB_ID_FAM_4		0x40u
57 #define MCHP_GCFG_SUB_ID_FAM_5		0x50u
58 #define MCHP_GCFG_SUB_ID_FAM_6		0x60u
59 #define MCHP_GCFG_SUB_ID_FAM_7		0x70u
61 #define MCHP_GCFG_DEV_ID_LSB_OFS	0x1eu
62 #define MCHP_GCFG_DEV_ID_MSB_OFS	0x1fu
63 #define MCHP_GCFG_DEV_ID_172X		0x0022u
64 #define MCHP_GCFG_DEV_ID_172X_LSB	0x22u
65 #define MCHP_GCFG_DEV_ID_172X_MSB	0x00u
68 #define MCHP_GCFG_DEVID_1723_144	0x00223400u
69 #define MCHP_GCFG_DEVID_1727_144	0x00227400u
71 #define MCHP_GCFG_DID_1721_176		0x00222700u
72 #define MCHP_GCFG_DID_1723_176		0x00223700u
73 #define MCHP_GCFG_DID_1727_176		0x00227700u
76 #define MCHP_CCFG_LEGACY_DID_REG_OFS	0x20u
77 #define MCHP_GCFG_LEGACY_DEV_ID		0xfeu
79 /* Host access via configuration port (default I/O locations 0x2E/0x2F) */
80 #define MCHP_HOST_CFG_INDEX_IO_DFLT	0x2eu
81 #define MCHP_HOST_CFG_DATA_IO_DFLT	0x2fu
82 #define MCHP_HOST_CFG_UNLOCK		0x55u
83 #define MCHP_HOST_CFG_LOCK		0xaau
86 #define MCHP_HOST_CFG_LD_ACTIVATE_IDX	0x30u
87 #define MCHP_HOST_CFG_LD_BASE_ADDR_IDX	0x34u
88 #define MCHP_HOST_CFG_LD_CFG_SEL_IDX	0xf0u