Lines Matching refs:ECREG
14 #define ECREG(x) x macro
20 #define ECREG(x) (*((volatile unsigned char *)(x))) macro
50 #define IT8XXX2_GCTRL_EIDSR ECREG(IT8XXX2_GCTRL_BASE + 0x31)
51 #define IT8XXX2_GCTRL_PMER3 ECREG(IT8XXX2_GCTRL_BASE + 0x46)
59 #define IT8XXX2_JTAG_PINS_BASE ECREG(0xF01660)
60 #define IT8XXX2_JTAG_VOLT_SET ECREG(0xF01648)
62 #define IT8XXX2_JTAG_PINS_BASE ECREG(0xF01610)
63 #define IT8XXX2_JTAG_VOLT_SET ECREG(0xF016e9)
69 #define IT8XXX2_EGPIO_EGCR ECREG(IT8XXX2_EGPIO_BASE + 0x04)
85 #define ISR0 ECREG(EC_REG_BASE_ADDR + 0x3F00)
86 #define ISR1 ECREG(EC_REG_BASE_ADDR + 0x3F01)
87 #define ISR2 ECREG(EC_REG_BASE_ADDR + 0x3F02)
88 #define ISR3 ECREG(EC_REG_BASE_ADDR + 0x3F03)
89 #define ISR4 ECREG(EC_REG_BASE_ADDR + 0x3F14)
90 #define ISR5 ECREG(EC_REG_BASE_ADDR + 0x3F18)
91 #define ISR6 ECREG(EC_REG_BASE_ADDR + 0x3F1C)
92 #define ISR7 ECREG(EC_REG_BASE_ADDR + 0x3F20)
93 #define ISR8 ECREG(EC_REG_BASE_ADDR + 0x3F24)
94 #define ISR9 ECREG(EC_REG_BASE_ADDR + 0x3F28)
95 #define ISR10 ECREG(EC_REG_BASE_ADDR + 0x3F2C)
96 #define ISR11 ECREG(EC_REG_BASE_ADDR + 0x3F30)
97 #define ISR12 ECREG(EC_REG_BASE_ADDR + 0x3F34)
98 #define ISR13 ECREG(EC_REG_BASE_ADDR + 0x3F38)
99 #define ISR14 ECREG(EC_REG_BASE_ADDR + 0x3F3C)
100 #define ISR15 ECREG(EC_REG_BASE_ADDR + 0x3F40)
101 #define ISR16 ECREG(EC_REG_BASE_ADDR + 0x3F44)
102 #define ISR17 ECREG(EC_REG_BASE_ADDR + 0x3F48)
103 #define ISR18 ECREG(EC_REG_BASE_ADDR + 0x3F4C)
104 #define ISR19 ECREG(EC_REG_BASE_ADDR + 0x3F50)
105 #define ISR20 ECREG(EC_REG_BASE_ADDR + 0x3F54)
106 #define ISR21 ECREG(EC_REG_BASE_ADDR + 0x3F58)
107 #define ISR22 ECREG(EC_REG_BASE_ADDR + 0x3F5C)
108 #define ISR23 ECREG(EC_REG_BASE_ADDR + 0x3F90)
110 #define IER0 ECREG(EC_REG_BASE_ADDR + 0x3F04)
111 #define IER1 ECREG(EC_REG_BASE_ADDR + 0x3F05)
112 #define IER2 ECREG(EC_REG_BASE_ADDR + 0x3F06)
113 #define IER3 ECREG(EC_REG_BASE_ADDR + 0x3F07)
114 #define IER4 ECREG(EC_REG_BASE_ADDR + 0x3F15)
115 #define IER5 ECREG(EC_REG_BASE_ADDR + 0x3F19)
116 #define IER6 ECREG(EC_REG_BASE_ADDR + 0x3F1D)
117 #define IER7 ECREG(EC_REG_BASE_ADDR + 0x3F21)
118 #define IER8 ECREG(EC_REG_BASE_ADDR + 0x3F25)
119 #define IER9 ECREG(EC_REG_BASE_ADDR + 0x3F29)
120 #define IER10 ECREG(EC_REG_BASE_ADDR + 0x3F2D)
121 #define IER11 ECREG(EC_REG_BASE_ADDR + 0x3F31)
122 #define IER12 ECREG(EC_REG_BASE_ADDR + 0x3F35)
123 #define IER13 ECREG(EC_REG_BASE_ADDR + 0x3F39)
124 #define IER14 ECREG(EC_REG_BASE_ADDR + 0x3F3D)
125 #define IER15 ECREG(EC_REG_BASE_ADDR + 0x3F41)
126 #define IER16 ECREG(EC_REG_BASE_ADDR + 0x3F45)
127 #define IER17 ECREG(EC_REG_BASE_ADDR + 0x3F49)
128 #define IER18 ECREG(EC_REG_BASE_ADDR + 0x3F4D)
129 #define IER19 ECREG(EC_REG_BASE_ADDR + 0x3F51)
130 #define IER20 ECREG(EC_REG_BASE_ADDR + 0x3F55)
131 #define IER21 ECREG(EC_REG_BASE_ADDR + 0x3F59)
132 #define IER22 ECREG(EC_REG_BASE_ADDR + 0x3F5D)
133 #define IER23 ECREG(EC_REG_BASE_ADDR + 0x3F91)
135 #define IELMR0 ECREG(EC_REG_BASE_ADDR + 0x3F08)
136 #define IELMR1 ECREG(EC_REG_BASE_ADDR + 0x3F09)
137 #define IELMR2 ECREG(EC_REG_BASE_ADDR + 0x3F0A)
138 #define IELMR3 ECREG(EC_REG_BASE_ADDR + 0x3F0B)
139 #define IELMR4 ECREG(EC_REG_BASE_ADDR + 0x3F16)
140 #define IELMR5 ECREG(EC_REG_BASE_ADDR + 0x3F1A)
141 #define IELMR6 ECREG(EC_REG_BASE_ADDR + 0x3F1E)
142 #define IELMR7 ECREG(EC_REG_BASE_ADDR + 0x3F22)
143 #define IELMR8 ECREG(EC_REG_BASE_ADDR + 0x3F26)
144 #define IELMR9 ECREG(EC_REG_BASE_ADDR + 0x3F2A)
145 #define IELMR10 ECREG(EC_REG_BASE_ADDR + 0x3F2E)
146 #define IELMR11 ECREG(EC_REG_BASE_ADDR + 0x3F32)
147 #define IELMR12 ECREG(EC_REG_BASE_ADDR + 0x3F36)
148 #define IELMR13 ECREG(EC_REG_BASE_ADDR + 0x3F3A)
149 #define IELMR14 ECREG(EC_REG_BASE_ADDR + 0x3F3E)
150 #define IELMR15 ECREG(EC_REG_BASE_ADDR + 0x3F42)
151 #define IELMR16 ECREG(EC_REG_BASE_ADDR + 0x3F46)
152 #define IELMR17 ECREG(EC_REG_BASE_ADDR + 0x3F4A)
153 #define IELMR18 ECREG(EC_REG_BASE_ADDR + 0x3F4E)
154 #define IELMR19 ECREG(EC_REG_BASE_ADDR + 0x3F52)
155 #define IELMR20 ECREG(EC_REG_BASE_ADDR + 0x3F56)
156 #define IELMR21 ECREG(EC_REG_BASE_ADDR + 0x3F5A)
157 #define IELMR22 ECREG(EC_REG_BASE_ADDR + 0x3F5E)
158 #define IELMR23 ECREG(EC_REG_BASE_ADDR + 0x3F92)
160 #define IPOLR0 ECREG(EC_REG_BASE_ADDR + 0x3F0C)
161 #define IPOLR1 ECREG(EC_REG_BASE_ADDR + 0x3F0D)
162 #define IPOLR2 ECREG(EC_REG_BASE_ADDR + 0x3F0E)
163 #define IPOLR3 ECREG(EC_REG_BASE_ADDR + 0x3F0F)
164 #define IPOLR4 ECREG(EC_REG_BASE_ADDR + 0x3F17)
165 #define IPOLR5 ECREG(EC_REG_BASE_ADDR + 0x3F1B)
166 #define IPOLR6 ECREG(EC_REG_BASE_ADDR + 0x3F1F)
167 #define IPOLR7 ECREG(EC_REG_BASE_ADDR + 0x3F23)
168 #define IPOLR8 ECREG(EC_REG_BASE_ADDR + 0x3F27)
169 #define IPOLR9 ECREG(EC_REG_BASE_ADDR + 0x3F2B)
170 #define IPOLR10 ECREG(EC_REG_BASE_ADDR + 0x3F2F)
171 #define IPOLR11 ECREG(EC_REG_BASE_ADDR + 0x3F33)
172 #define IPOLR12 ECREG(EC_REG_BASE_ADDR + 0x3F37)
173 #define IPOLR13 ECREG(EC_REG_BASE_ADDR + 0x3F3B)
174 #define IPOLR14 ECREG(EC_REG_BASE_ADDR + 0x3F3F)
175 #define IPOLR15 ECREG(EC_REG_BASE_ADDR + 0x3F43)
176 #define IPOLR16 ECREG(EC_REG_BASE_ADDR + 0x3F47)
177 #define IPOLR17 ECREG(EC_REG_BASE_ADDR + 0x3F4B)
178 #define IPOLR18 ECREG(EC_REG_BASE_ADDR + 0x3F4F)
179 #define IPOLR19 ECREG(EC_REG_BASE_ADDR + 0x3F53)
180 #define IPOLR20 ECREG(EC_REG_BASE_ADDR + 0x3F57)
181 #define IPOLR21 ECREG(EC_REG_BASE_ADDR + 0x3F5B)
182 #define IPOLR22 ECREG(EC_REG_BASE_ADDR + 0x3F5F)
183 #define IPOLR23 ECREG(EC_REG_BASE_ADDR + 0x3F93)
185 #define IVECT ECREG(EC_REG_BASE_ADDR + 0x3F10)
194 #define GPCRF4 ECREG(EC_REG_BASE_ADDR + 0x163C)
195 #define GPCRF5 ECREG(EC_REG_BASE_ADDR + 0x163D)
196 #define GPCRH1 ECREG(EC_REG_BASE_ADDR + 0x1649)
197 #define GPCRH2 ECREG(EC_REG_BASE_ADDR + 0x164A)
199 #define GPCRF4 ECREG(EC_REG_BASE_ADDR + 0x168C)
200 #define GPCRF5 ECREG(EC_REG_BASE_ADDR + 0x168D)
201 #define GPCRH1 ECREG(EC_REG_BASE_ADDR + 0x1699)
202 #define GPCRH2 ECREG(EC_REG_BASE_ADDR + 0x169A)
419 #define IT8XXX2_EXT_CTRLX(n) ECREG(IT8XXX2_EXT_TIMER_BASE + (n << 3))
420 #define IT8XXX2_EXT_PSRX(n) ECREG(IT8XXX2_EXT_TIMER_BASE + 0x01 + (n << 3))
1138 #define IT8XXX2_GPIO_GCRX(offset) ECREG(IT8XXX2_GPIO_BASE + (offset))
1162 #define IT8XXX2_GPIO_GPCRP0 ECREG(IT8XXX2_GPIO2_BASE + 0x18)
1163 #define IT8XXX2_GPIO_GPCRP1 ECREG(IT8XXX2_GPIO2_BASE + 0x19)
1272 #define IT8XXX2_ECPM_PLLCTRL ECREG(IT8XXX2_ECPM_BASE + 0x03)
1273 #define IT8XXX2_ECPM_AUTOCG ECREG(IT8XXX2_ECPM_BASE + 0x04)
1274 #define IT8XXX2_ECPM_CGCTRL3R ECREG(IT8XXX2_ECPM_BASE + 0x05)
1275 #define IT8XXX2_ECPM_PLLFREQR ECREG(IT8XXX2_ECPM_BASE + 0x06)
1276 #define IT8XXX2_ECPM_PLLCSS ECREG(IT8XXX2_ECPM_BASE + 0x08)
1277 #define IT8XXX2_ECPM_SCDCR0 ECREG(IT8XXX2_ECPM_BASE + 0x0c)
1278 #define IT8XXX2_ECPM_SCDCR1 ECREG(IT8XXX2_ECPM_BASE + 0x0d)
1279 #define IT8XXX2_ECPM_SCDCR2 ECREG(IT8XXX2_ECPM_BASE + 0x0e)
1280 #define IT8XXX2_ECPM_SCDCR3 ECREG(IT8XXX2_ECPM_BASE + 0x0f)
1281 #define IT8XXX2_ECPM_SCDCR4 ECREG(IT8XXX2_ECPM_BASE + 0x10)
1282 #define IT8XXX2_ECPM_PFACC0R ECREG(IT8XXX2_ECPM_BASE + 0x20)
1283 #define IT8XXX2_ECPM_PFACC1R ECREG(IT8XXX2_ECPM_BASE + 0x21)
1284 #define IT8XXX2_ECPM_PFACC2R ECREG(IT8XXX2_ECPM_BASE + 0x40)
1285 #define IT8XXX2_ECPM_LCOTF2 ECREG(IT8XXX2_ECPM_BASE + 0x54)
1286 #define IT8XXX2_ECPM_LCOCR ECREG(IT8XXX2_ECPM_BASE + 0x55)
1287 #define IT8XXX2_ECPM_LCOCR1 ECREG(IT8XXX2_ECPM_BASE + 0x57)
1303 #define IT8XXX2_SMB_4P7USL ECREG(IT8XXX2_SMB_BASE + 0x00)
1304 #define IT8XXX2_SMB_4P0USL ECREG(IT8XXX2_SMB_BASE + 0x01)
1305 #define IT8XXX2_SMB_300NS ECREG(IT8XXX2_SMB_BASE + 0x02)
1306 #define IT8XXX2_SMB_250NS ECREG(IT8XXX2_SMB_BASE + 0x03)
1307 #define IT8XXX2_SMB_25MS ECREG(IT8XXX2_SMB_BASE + 0x04)
1308 #define IT8XXX2_SMB_45P3USL ECREG(IT8XXX2_SMB_BASE + 0x05)
1309 #define IT8XXX2_SMB_45P3USH ECREG(IT8XXX2_SMB_BASE + 0x06)
1310 #define IT8XXX2_SMB_4P7A4P0H ECREG(IT8XXX2_SMB_BASE + 0x07)
1311 #define IT8XXX2_SMB_SLVISELR ECREG(IT8XXX2_SMB_BASE + 0x08)
1312 #define IT8XXX2_SMB_SCLKTS(ch) ECREG(IT8XXX2_SMB_BASE + 0x09 + ch)
1313 #define IT8XXX2_SMB_MSTFCTRL1 ECREG(IT8XXX2_SMB_BASE + 0x0D)
1314 #define IT8XXX2_SMB_MSTFSTS1 ECREG(IT8XXX2_SMB_BASE + 0x0E)
1315 #define IT8XXX2_SMB_MSTFCTRL2 ECREG(IT8XXX2_SMB_BASE + 0x0F)
1316 #define IT8XXX2_SMB_MSTFSTS2 ECREG(IT8XXX2_SMB_BASE + 0x10)
1317 #define IT8XXX2_SMB_SMB45CHS ECREG(IT8XXX2_SMB_BASE + 0x11)
1318 #define IT8XXX2_SMB_I2CW2RF ECREG(IT8XXX2_SMB_BASE + 0x12)
1319 #define IT8XXX2_SMB_IWRFISTA ECREG(IT8XXX2_SMB_BASE + 0x13)
1320 #define IT8XXX2_SMB_SMB01CHS ECREG(IT8XXX2_SMB_BASE + 0x20)
1321 #define IT8XXX2_SMB_SMB23CHS ECREG(IT8XXX2_SMB_BASE + 0x21)
1322 #define IT8XXX2_SMB_SFFCTL ECREG(IT8XXX2_SMB_BASE + 0x55)
1323 #define IT8XXX2_SMB_HOSTA(base) ECREG(base + 0x00)
1324 #define IT8XXX2_SMB_HOCTL(base) ECREG(base + 0x01)
1325 #define IT8XXX2_SMB_HOCMD(base) ECREG(base + 0x02)
1326 #define IT8XXX2_SMB_TRASLA(base) ECREG(base + 0x03)
1327 #define IT8XXX2_SMB_D0REG(base) ECREG(base + 0x04)
1328 #define IT8XXX2_SMB_D1REG(base) ECREG(base + 0x05)
1329 #define IT8XXX2_SMB_HOBDB(base) ECREG(base + 0x06)
1330 #define IT8XXX2_SMB_PECERC(base) ECREG(base + 0x07)
1331 #define IT8XXX2_SMB_SMBPCTL(base) ECREG(base + 0x0A)
1332 #define IT8XXX2_SMB_HOCTL2(base) ECREG(base + 0x10)
1334 #define IT8XXX2_SMB_SLVISEL ECREG(IT8XXX2_SMB_BASE + 0x08)
1335 #define IT8XXX2_SMB_SMB01CHS ECREG(IT8XXX2_SMB_BASE + 0x09)
1336 #define IT8XXX2_SMB_SMB23CHS ECREG(IT8XXX2_SMB_BASE + 0x0A)
1337 #define IT8XXX2_SMB_SMB45CHS ECREG(IT8XXX2_SMB_BASE + 0x0B)
1338 #define IT8XXX2_SMB_SCLKTS_BRGS ECREG(IT8XXX2_SMB_BASE + 0x80)
1339 #define IT8XXX2_SMB_SCLKTS_BRGM ECREG(IT8XXX2_SMB_BASE + 0x81)
1340 #define IT8XXX2_SMB_CHSBRG ECREG(IT8XXX2_SMB_BASE + 0x82)
1341 #define IT8XXX2_SMB_CHSMOT ECREG(IT8XXX2_SMB_BASE + 0x83)
1353 #define IT8XXX2_I2C_DRR(base) ECREG(base + 0x00)
1354 #define IT8XXX2_I2C_PSR(base) ECREG(base + 0x01)
1355 #define IT8XXX2_I2C_HSPR(base) ECREG(base + 0x02)
1356 #define IT8XXX2_I2C_STR(base) ECREG(base + 0x03)
1357 #define IT8XXX2_I2C_DHTR(base) ECREG(base + 0x04)
1358 #define IT8XXX2_I2C_TOR(base) ECREG(base + 0x05)
1359 #define IT8XXX2_I2C_DTR(base) ECREG(base + 0x08)
1360 #define IT8XXX2_I2C_CTR(base) ECREG(base + 0x09)
1361 #define IT8XXX2_I2C_CTR1(base) ECREG(base + 0x0A)
1362 #define IT8XXX2_I2C_BYTE_CNT_H(base) ECREG(base + 0x0B)
1363 #define IT8XXX2_I2C_BYTE_CNT_L(base) ECREG(base + 0x0C)
1364 #define IT8XXX2_I2C_IRQ_ST(base) ECREG(base + 0x0D)
1365 #define IT8XXX2_I2C_IDR(base) ECREG(base + 0x06)
1366 #define IT8XXX2_I2C_TOS(base) ECREG(base + 0x07)
1367 #define IT8XXX2_I2C_SLV_NUM_H(base) ECREG(base + 0x10)
1368 #define IT8XXX2_I2C_SLV_NUM_L(base) ECREG(base + 0x11)
1369 #define IT8XXX2_I2C_STR2(base) ECREG(base + 0x12)
1370 #define IT8XXX2_I2C_NST(base) ECREG(base + 0x13)
1371 #define IT8XXX2_I2C_TO_ARB_ST(base) ECREG(base + 0x18)
1372 #define IT8XXX2_I2C_ERR_ST(base) ECREG(base + 0x19)
1373 #define IT8XXX2_I2C_FST(base) ECREG(base + 0x1B)
1374 #define IT8XXX2_I2C_EM(base) ECREG(base + 0x1C)
1375 #define IT8XXX2_I2C_MODE_SEL(base) ECREG(base + 0x1D)
1376 #define IT8XXX2_I2C_IDR2(base) ECREG(base + 0x1F)
1377 #define IT8XXX2_I2C_CTR2(base) ECREG(base + 0x20)
1378 #define IT8XXX2_I2C_RAMHA(base) ECREG(base + 0x23)
1379 #define IT8XXX2_I2C_RAMLA(base) ECREG(base + 0x24)
1380 #define IT8XXX2_I2C_RAMHA2(base) ECREG(base + 0x2C)
1381 #define IT8XXX2_I2C_RAMLA2(base) ECREG(base + 0x2D)
1382 #define IT8XXX2_I2C_CMD_ADDH(base) ECREG(base + 0x25)
1383 #define IT8XXX2_I2C_CMD_ADDL(base) ECREG(base + 0x26)
1384 #define IT8XXX2_I2C_RAMH2A(base) ECREG(base + 0x50)
1385 #define IT8XXX2_I2C_CMD_ADDH2(base) ECREG(base + 0x52)
1480 #define IT83XX_GCTRL_CHIPID1 ECREG(IT83XX_GCTRL_BASE + 0x85)
1481 #define IT83XX_GCTRL_CHIPID2 ECREG(IT83XX_GCTRL_BASE + 0x86)
1482 #define IT83XX_GCTRL_CHIPVER ECREG(IT83XX_GCTRL_BASE + 0x02)
1483 #define IT83XX_GCTRL_MCCR3 ECREG(IT83XX_GCTRL_BASE + 0x20)
1485 #define IT83XX_GCTRL_EWPR0PFH(i) ECREG(IT83XX_GCTRL_BASE + 0x60 + i)
1486 #define IT83XX_GCTRL_EWPR0PFD(i) ECREG(IT83XX_GCTRL_BASE + 0xA0 + i)
1487 #define IT83XX_GCTRL_EWPR0PFEC(i) ECREG(IT83XX_GCTRL_BASE + 0xC0 + i)
1496 #define IT83XX_SPI_SPISGCR ECREG(IT83XX_SPI_BASE + 0x00)
1498 #define IT83XX_SPI_TXRXFAR ECREG(IT83XX_SPI_BASE + 0x01)
1502 #define IT83XX_SPI_TXFCR ECREG(IT83XX_SPI_BASE + 0x02)
1506 #define IT83XX_SPI_GCR2 ECREG(IT83XX_SPI_BASE + 0x03)
1510 #define IT83XX_SPI_IMR ECREG(IT83XX_SPI_BASE + 0x04)
1514 #define IT83XX_SPI_ISR ECREG(IT83XX_SPI_BASE + 0x05)
1515 #define IT83XX_SPI_TXFSR ECREG(IT83XX_SPI_BASE + 0x06)
1517 #define IT83XX_SPI_RXFSR ECREG(IT83XX_SPI_BASE + 0x07)
1521 #define IT83XX_SPI_SPISRDR ECREG(IT83XX_SPI_BASE + 0x0b)
1523 #define IT83XX_SPI_FCR ECREG(IT83XX_SPI_BASE + 0x09)
1528 #define IT83XX_SPI_FTCB0R ECREG(IT83XX_SPI_BASE + 0x18)
1529 #define IT83XX_SPI_FTCB1R ECREG(IT83XX_SPI_BASE + 0x19)
1530 #define IT83XX_SPI_TCCB0 ECREG(IT83XX_SPI_BASE + 0x1A)
1531 #define IT83XX_SPI_TCCB1 ECREG(IT83XX_SPI_BASE + 0x1B)
1532 #define IT83XX_SPI_HPR2 ECREG(IT83XX_SPI_BASE + 0x1E)
1533 #define IT83XX_SPI_EMMCBMR ECREG(IT83XX_SPI_BASE + 0x21)
1535 #define IT83XX_SPI_RX_VLISMR ECREG(IT83XX_SPI_BASE + 0x26)
1537 #define IT83XX_SPI_RX_VLISR ECREG(IT83XX_SPI_BASE + 0x27)