Lines Matching +full:host +full:- +full:slave
3 * SPDX-License-Identifier: Apache-2.0
48 /* --- General Control (GCTRL) --- */
52 /* RISC-V JTAG Debug Interface Enable */
54 /* RISC-V JTAG Debug Interface Selection */
67 /* --- External GPIO Control (EGPIO) --- */
265 /* 0x049: PWM Output Open-Drain Enable */
280 /* --- Wake-Up Control (WUC) --- */
284 /* TODO: should a defined interface for configuring wake-up interrupts */
442 * 24-bit timers: external timer 3, 5, and 7
443 * 32-bit timers: external timer 4, 6, and 8
463 /* 0x00: Host Status */
465 /* 0x01: Host Control */
467 /* 0x02: Host Command */
469 /* 0x03: Host Target Address */
471 /* 0x04: Host Write Length */
473 /* 0x05: Host Read Length */
475 /* 0x06: Host Write Data */
477 /* 0x07: Host Read Data */
479 /* 0x08: Host Control 2 */
620 /* From BXh to BDh are EP FIFO 1-3 Control 0/1 Registers, and their
653 /* 0xB8 ~ 0xBD EP FIFO 1-3 Control 0/1 Registers */
752 /* 0x00: Host TX Contrl Register */
754 /* 0x01: Host TX Transaction Type Register */
756 /* 0x02: Host TX Line Control Register */
758 /* 0x03: Host TX SOF Enable Register */
760 /* 0x04: Host TX Address Register */
762 /* 0x05: Host TX EP Number Register */
764 /* 0x06: Host Frame Number MSP Register */
766 /* 0x07: Host Frame Number LSP Register */
768 /* 0x08: Host Interrupt Status Register */
770 /* 0x09: Host Interrupt Mask Register */
772 /* 0x0A: Host RX Status Register */
774 /* 0x0B: Host RX PID Register */
780 /* 0x0E: Host RX Connect State Register */
782 /* 0x0F: Host SOF Timer MSB Register */
784 /* 0x10 ~ 0x1F: Reserved Registers 10h - 1Fh */
786 /* 0x20: Host RX FIFO Data Port Register */
788 /* 0x21: Host RX FIFO DMA Input Data Count Register */
790 /* 0x22: Host TX FIFO Data Count MSB Register */
792 /* 0x23: Host TX FIFO Data Count LSB Register */
794 /* 0x24: Host RX FIFO Data Port Register */
796 /* 0x25 ~ 0x2F: Reserved Registers 25h - 2Fh */
798 /* 0x30: Host TX FIFO Data Port Register */
800 /* 0x31 ~ 0x3F: Reserved Registers 31h - 3Fh */
802 /* 0x40 ~ 0x4F: Endpoint Registers 40h - 4Fh */
818 /* 0x57 ~ 0x5F: Reserved Registers 57h - 5Fh */
820 /* 0x60 ~ 0xDF: EP FIFO Registers 60h - DFh */
822 /* 0xE0: Host/Device Control Register */
824 /* 0xE1 ~ 0xE3: Reserved Registers E1h - E3h */
828 /* 0xE5 ~ 0xE7: Reserved Registers E5h - E7h */
883 /* 0x3B: EC-Indirect memory address 0 */
885 /* 0x3C: EC-Indirect memory address 1 */
887 /* 0x3D: EC-Indirect memory address 2 */
889 /* 0x3E: EC-Indirect memory address 3 */
891 /* 0x3F: EC-Indirect memory data */
900 /* 0x5A: Host RAM Window Control */
902 /* 0x5B: Host RAM Window 0 Base Address [11:4] */
904 /* 0x5C: Host RAM Window 1 Base Address [11:4] */
906 /* 0x5D: Host RAM Window 0 Access Allow Size */
908 /* 0x5E: Host RAM Window 1 Access Allow Size */
918 /* EC-Indirect read internal flash */
920 /* Enable EC-indirect page program command */
934 /* Host RAM Window x Write Protect Enable (All protected) */
951 /* 0x01-D0: Reserved1 */
967 /* 0xD8-0xDF: Reserved2 */
989 /* 0xEA-0xEC: Reserved4 */
1034 /* 0x01-0x0F: Reserved1 */
1082 /* 0x27-0x28: Reserved4 */
1086 /* 0x2A-0x2C: Reserved5 */
1128 * configured as tri-state.
1134 /* --- GPIO --- */
1173 /* Data structure to define ADC channel 13-16 control registers. */
1196 /* 0x06-0x17: Reserved1 */
1202 /* 0x1a-0x43: Reserved2 */
1206 /* 0x45-0x54: Reserved2-1 */
1208 /* 0x55: ADC Input Voltage Mapping Full-Scale Code Selection 1 */
1210 /* 0x56: ADC Input Voltage Mapping Full-Scale Code Selection 2 */
1212 /* 0x57: ADC Input Voltage Mapping Full-Scale Code Selection 3 */
1214 /* 0x58-0x5f: Reserved3 */
1216 /* 0x60-0x6b: ADC channel 13~16 controller */
1220 /* 0x6d-0xef: Reserved4 */
1344 /* 0x80: SMCLK Timing Setting Register Bridge Slave */
1388 /* 0x09-0xB: SMCLK Timing Setting */
1415 /* 0x41 0x81 0xC1: Host Control */
1421 /* 0x43 0x83 0xC3: Transmit Slave Address */
1426 /* 0x50 0x90 0xD0: Host Control 2 */
1432 /* 0x55: Slave A FIFO Control */
1477 /* --- General Control (GCTRL) --- */
1550 /* 0x00-0x01: Reserved_00_01 */
1556 /* 0x04-0x05: Reserved_04_05 */
1560 /* 0x07-0x09: Reserved_07_09 */
1570 /* 0x0E-0x0F: reserved_0e_0f */
1576 /* 0x12-0x1B: reserved_12_1b */
1580 /* 0x1D-0x1F: reserved_1d_1f */
1586 /* 0x22-0x2F: reserved_22_2f */
1594 /* 0x33: Pin Multi-function Enable 2 */
1596 /* 0x34-0x36: Reserved_34_36 */
1600 /* 0x38-0x40: Reserved_38_40 */
1604 /* 0x42-0x43: Reserved_42_43 */
1610 /* 0x46: Pin Multi-function Enable 3 */
1612 /* 0x47-0x4A: reserved_47_4a */
1618 /* 0x4D-0x4F: reserved_4d_4f */
1628 /* 0x54-0x5C: reserved_54_5c */
1632 /* 0x5E-0x84: reserved_5e_84 */
1669 /* 0x46: Pin Multi-function Enable 3 */
1682 /* USB Pad Power-On Enable */
1687 * bit[7-6] = 1: The VCC power status is treated as power-on.
1704 * (22xxh) Battery-backed SRAM (BRAM) registers
1725 /* 0x00: Indirect Host I/O Address Register */
1727 /* 0x01: Indirect Host Data Register */
1729 /* 0x02: Lock Super I/O Host Access Register */
1733 /* 0x04: EC to I-Bus Modules Access Enable Register */
1735 /* 0x05: I-Bus Control Register */
1739 /* Index list of the host interface registers of PNPCFG */
1771 /* Interrupt Request Number and Wake-Up on IRQ Enabled */
1798 /* System Wake-Up Control */
1808 /* RTC-like Timer */
1842 /* EC to I-Bus Access Enabled */
1844 /* EC Read from I-Bus */
1846 /* EC Write to I-Bus */
1857 /* 0x00: KBC Host Interface Control Register */
1865 /* 0x04: KBC Host Interface Keyboard/Mouse Status Register */
1869 /* 0x06: KBC Host Interface Keyboard Data Output Register */
1873 /* 0x08: KBC Host Interface Mouse Data Output Register */
1877 /* 0x0a: KBC Host Interface Keyboard/Mouse Data Input Register */
1907 /* 0x00: Host Interface PM Channel 1 Status */
1909 /* 0x01: Host Interface PM Channel 1 Data Out Port */
1911 /* 0x02: Host Interface PM Channel 1 Data Out Port with SCI# */
1913 /* 0x03: Host Interface PM Channel 1 Data Out Port with SMI# */
1915 /* 0x04: Host Interface PM Channel 1 Data In Port */
1917 /* 0x05: Host Interface PM Channel 1 Data In Port with SCI# */
1919 /* 0x06: Host Interface PM Channel 1 Control */
1921 /* 0x07: Host Interface PM Channel 1 Interrupt Control */
1923 /* 0x08: Host Interface PM Channel 1 Interrupt Enable */
1925 /* 0x09-0x0f: Reserved1 */
1927 /* 0x10: Host Interface PM Channel 2 Status */
1929 /* 0x11: Host Interface PM Channel 2 Data Out Port */
1931 /* 0x12: Host Interface PM Channel 2 Data Out Port with SCI# */
1933 /* 0x13: Host Interface PM Channel 2 Data Out Port with SMI# */
1935 /* 0x14: Host Interface PM Channel 2 Data In Port */
1937 /* 0x15: Host Interface PM Channel 2 Data In Port with SCI# */
1939 /* 0x16: Host Interface PM Channel 2 Control */
1941 /* 0x17: Host Interface PM Channel 2 Interrupt Control */
1943 /* 0x18: Host Interface PM Channel 2 Interrupt Enable */
1947 /* 0x1a-0x1f: Reserved2 */
1949 /* 0x20-0xff: Reserved3 */
1983 * eSPI slave registers
1986 /* 0x00-0x03: Reserved1 */
2038 /* 0x18: Channel 3 Capabilities and Configuration 2-0 */
2040 /* 0x19: Channel 3 Capabilities and Configuration 2-1 */
2042 /* 0x1A: Channel 3 Capabilities and Configuration 2-2 */
2044 /* 0x1B: Channel 3 Capabilities and Configuration 2-3 */
2047 /* 0x1c-0x1f: Reserved2 */
2049 /* 0x20-0x8f: Reserved3 */
2068 /* 0x98-0x9f: Reserved4 */
2079 /* 0xa4-0xaf: Reserved5 */
2090 /* 0xb4-0xb5: Reserved6 */
2098 /* 0xb9-0xbf: Reserved7 */
2105 /* 0xc2-0xc3: Reserved8 */
2109 /* 0xc5-0xcf: Reserved9 */
2134 /* 0x00-0x7f: VW index */
2136 /* 0x80-0x8f: Reserved1 */
2154 /* 0x98-0x99: Reserved3 */
2163 /* 0x00-0x3f: PUT_PC Data Byte 0-63 */
2165 /* 0x40-0x7f: Reserved1 */
2167 /* 0x80-0xcf: PUT_OOB Data Byte 0-79 */
2175 /* 0x00-0x4f: Upstream Data Byte 0-79 */
2177 /* 0x50-0x7f: Reserved1 */
2179 /* 0x80-0xbf: PUT_FLASH_NP Data Byte 0-63 */
2188 * (3Axxh) SPI Slave Controller (SPISC) registers
2193 /* 0x00: SPI Slave General Control */
2199 /* 0x03: SPI Slave General Control 2 */
2215 /* 0x0B: SPI Slave Response Data / CPU Write Tx FIFO Data Byte3 */
2225 /* 0x10-0x17: Reserved1 */
2235 /* 0x1C-0x1D: Reserved2 */
2239 /* 0x1F-0x25: Reserved3 */
2249 /* 0x00: SPI Slave General Control */
2258 /* 0x03: SPI Slave General Control 2 */