Lines Matching +full:vcc +full:- +full:3

3  * SPDX-License-Identifier: Apache-2.0
48 /* --- General Control (GCTRL) --- */
52 /* RISC-V JTAG Debug Interface Enable */
54 /* RISC-V JTAG Debug Interface Selection */
67 /* --- External GPIO Control (EGPIO) --- */
240 volatile uint8_t Reserved4[3];
265 /* 0x049: PWM Output Open-Drain Enable */
274 #define IT8XXX2_PWM_T0DVS BIT(3)
280 /* --- Wake-Up Control (WUC) --- */
284 /* TODO: should a defined interface for configuring wake-up interrupts */
392 #define IT8XXX2_WDT_LEWDCNTL BIT(3)
403 #define IT8XXX2_WDT_ET2TC BIT(3)
409 /* External Timer 3~8 control */
413 #define IT8XXX2_EXT_ETXCOMB BIT(3)
419 #define IT8XXX2_EXT_CTRLX(n) ECREG(IT8XXX2_EXT_TIMER_BASE + (n << 3))
420 #define IT8XXX2_EXT_PSRX(n) ECREG(IT8XXX2_EXT_TIMER_BASE + 0x01 + (n << 3))
422 (n << 3))
442 * 24-bit timers: external timer 3, 5, and 7
443 * 32-bit timers: external timer 4, 6, and 8
503 #define EP_EXT_REGS_DX 3
582 * 3 Reserved
620 /* From BXh to BDh are EP FIFO 1-3 Control 0/1 Registers, and their
638 * 3 EP11 select FIFO1 as data buffer
653 /* 0xB8 ~ 0xBD EP FIFO 1-3 Control 0/1 Registers */
731 volatile uint8_t reserved_71_73_add_20[3];
784 /* 0x10 ~ 0x1F: Reserved Registers 10h - 1Fh */
796 /* 0x25 ~ 0x2F: Reserved Registers 25h - 2Fh */
800 /* 0x31 ~ 0x3F: Reserved Registers 31h - 3Fh */
802 /* 0x40 ~ 0x4F: Endpoint Registers 40h - 4Fh */
818 /* 0x57 ~ 0x5F: Reserved Registers 57h - 5Fh */
820 /* 0x60 ~ 0xDF: EP FIFO Registers 60h - DFh */
824 /* 0xE1 ~ 0xE3: Reserved Registers E1h - E3h */
825 volatile uint8_t reserved_e1_e3[3];
828 /* 0xE5 ~ 0xE7: Reserved Registers E5h - E7h */
829 volatile uint8_t reserved_e5_e7[3];
857 #define IT8XXX2_USBPD_CC_SELECT_RP_RESERVED (BIT(3) | BIT(2) | BIT(1))
858 #define IT8XXX2_USBPD_CC_SELECT_RP_DEF (BIT(3) | BIT(2))
859 #define IT8XXX2_USBPD_CC_SELECT_RP_1A5 BIT(3)
865 #define IT8XXX2_USBPD_CC1_DISCONNECT BIT(3)
883 /* 0x3B: EC-Indirect memory address 0 */
885 /* 0x3C: EC-Indirect memory address 1 */
887 /* 0x3D: EC-Indirect memory address 2 */
889 /* 0x3E: EC-Indirect memory address 3 */
891 /* 0x3F: EC-Indirect memory data */
918 /* EC-Indirect read internal flash */
920 /* Enable EC-indirect page program command */
921 #define IT8XXX2_SMFI_MASK_ECINDPP BIT(3)
925 #define IT8XXX2_SMFI_SCAR0H_ENABLE BIT(3)
951 /* 0x01-D0: Reserved1 */
967 /* 0xD8-0xDF: Reserved2 */
989 /* 0xEA-0xEC: Reserved4 */
990 volatile uint8_t reserved4[3];
1001 /* 0xF2: General Control 3 */
1034 /* 0x01-0x0F: Reserved1 */
1040 /* 0x12: General Control 3 */
1082 /* 0x27-0x28: Reserved4 */
1086 /* 0x2A-0x2C: Reserved5 */
1087 volatile uint8_t reserved5[3];
1128 * configured as tri-state.
1134 /* --- GPIO --- */
1173 /* Data structure to define ADC channel 13-16 control registers. */
1196 /* 0x06-0x17: Reserved1 */
1202 /* 0x1a-0x43: Reserved2 */
1206 /* 0x45-0x54: Reserved2-1 */
1208 /* 0x55: ADC Input Voltage Mapping Full-Scale Code Selection 1 */
1210 /* 0x56: ADC Input Voltage Mapping Full-Scale Code Selection 2 */
1212 /* 0x57: ADC Input Voltage Mapping Full-Scale Code Selection 3 */
1214 /* 0x58-0x5f: Reserved3 */
1216 /* 0x60-0x6b: ADC channel 13~16 controller */
1220 /* 0x6d-0xef: Reserved4 */
1230 #define IT8XXX2_ADC_AINITB BIT(3)
1250 #define IT8XXX2_VCMP_GPIO_ACTIVE_LOW BIT(3)
1265 CHIP_PLL_DEEP_DOZE = 3,
1388 /* 0x09-0xB: SMCLK Timing Setting */
1390 #define IT8XXX2_SMB_SMCLKS_400K 3
1400 #define IT8XXX2_SMB_FFEN BIT(3)
1418 #define IT8XXX2_SMB_SMCD_EXTND BIT(4) | BIT(3) | BIT(2)
1428 #define IT8XXX2_SMB_I2C_SW_EN BIT(3)
1446 #define IT8XXX2_I2C_ACK BIT(3)
1453 #define IT8XXX2_I2C_BYTE_CNT_ENABLE BIT(3)
1456 #define IT8XXX2_I2C_IDW_CLR BIT(3)
1462 #define IT8XXX2_I2C_NST_ID_NACK BIT(3)
1477 /* --- General Control (GCTRL) --- */
1500 #define IT83XX_SPI_CPURXF1A BIT(3)
1508 #define IT83XX_SPI_RXF1OC BIT(3)
1518 #define IT83XX_SPI_RXFFSM (BIT(4) | BIT(3))
1550 /* 0x00-0x01: Reserved_00_01 */
1556 /* 0x04-0x05: Reserved_04_05 */
1560 /* 0x07-0x09: Reserved_07_09 */
1561 volatile uint8_t reserved_07_09[3];
1570 /* 0x0E-0x0F: reserved_0e_0f */
1576 /* 0x12-0x1B: reserved_12_1b */
1580 /* 0x1D-0x1F: reserved_1d_1f */
1581 volatile uint8_t reserved_1d_1f[3];
1582 /* 0x20: Memory Controller Configuration 3 */
1586 /* 0x22-0x2F: reserved_22_2f */
1594 /* 0x33: Pin Multi-function Enable 2 */
1596 /* 0x34-0x36: Reserved_34_36 */
1597 volatile uint8_t reserved_34_36[3];
1600 /* 0x38-0x40: Reserved_38_40 */
1604 /* 0x42-0x43: Reserved_42_43 */
1610 /* 0x46: Pin Multi-function Enable 3 */
1612 /* 0x47-0x4A: reserved_47_4a */
1618 /* 0x4D-0x4F: reserved_4d_4f */
1619 volatile uint8_t reserved_4d_4f[3];
1628 /* 0x54-0x5C: reserved_54_5c */
1632 /* 0x5E-0x84: reserved_5e_84 */
1638 /* 0x87: Chip ID Byte 3 */
1652 #define IT8XXX2_GCTRL_UART1SD BIT(3)
1662 /* 0x20: Memory Controller Configuration 3 */
1669 /* 0x46: Pin Multi-function Enable 3 */
1679 #define IT8XXX2_GCTRL_ACP81 BIT(3)
1682 /* USB Pad Power-On Enable */
1686 * VCC Detector Option.
1687 * bit[7-6] = 1: The VCC power status is treated as power-on.
1688 * The VCC supply of eSPI and related functions (EC2I, KBC, PMC and
1689 * PECI). It means VCC should be logic high before using these
1690 * functions, or firmware treats VCC logic high.
1695 * bit[3] = 0: The reset source of PNPCFG is RSTPNP bit in RSTCH
1698 #define IT8XXX2_GCTRL_HGRST BIT(3)
1704 * (22xxh) Battery-backed SRAM (BRAM) registers
1733 /* 0x04: EC to I-Bus Modules Access Enable Register */
1735 /* 0x05: I-Bus Control Register */
1771 /* Interrupt Request Number and Wake-Up on IRQ Enabled */
1798 /* System Wake-Up Control */
1808 /* RTC-like Timer */
1818 /* Power Management I/F Channel 3 */
1842 /* EC to I-Bus Access Enabled */
1844 /* EC Read from I-Bus */
1846 /* EC Write to I-Bus */
1886 #define KBC_KBHISR_A2_ADDR BIT(3)
1895 #define KBC_KBHICR_IBFCIE BIT(3)
1925 /* 0x09-0x0f: Reserved1 */
1947 /* 0x1a-0x1f: Reserved2 */
1949 /* 0x20-0xff: Reserved3 */
1962 #define PMC_PM1STS_A2_ADDR BIT(3)
1986 /* 0x00-0x03: Reserved1 */
1995 /* 0x07: General Capabilities and Configuration 3 */
2005 /* 0x0B: Channel 0 Capabilities and Configuration 3 */
2015 /* 0x0F: Channel 1 Capabilities and Configuration 3 */
2025 /* 0x13: Channel 2 Capabilities and Configuration 3 */
2028 /* Channel 3 (Flash Access Channel) Capabilities and Configurations */
2029 /* 0x14: Channel 3 Capabilities and Configuration 0 */
2031 /* 0x15: Channel 3 Capabilities and Configuration 1 */
2033 /* 0x16: Channel 3 Capabilities and Configuration 2 */
2035 /* 0x17: Channel 3 Capabilities and Configuration 3 */
2037 /* Channel 3 Capabilities and Configurations 2 */
2038 /* 0x18: Channel 3 Capabilities and Configuration 2-0 */
2040 /* 0x19: Channel 3 Capabilities and Configuration 2-1 */
2042 /* 0x1A: Channel 3 Capabilities and Configuration 2-2 */
2044 /* 0x1B: Channel 3 Capabilities and Configuration 2-3 */
2047 /* 0x1c-0x1f: Reserved2 */
2049 /* 0x20-0x8f: Reserved3 */
2058 /* 0x93: eSPI PC Control 3 */
2068 /* 0x98-0x9f: Reserved4 */
2077 /* 0xa3: eSPI General Control 3 */
2079 /* 0xa4-0xaf: Reserved5 */
2088 /* 0xb3: eSPI Upstream Control 3 */
2090 /* 0xb4-0xb5: Reserved6 */
2098 /* 0xb9-0xbf: Reserved7 */
2105 /* 0xc2-0xc3: Reserved8 */
2109 /* 0xc5-0xcf: Reserved9 */
2118 /* 0xd3: eSPI SAFS Control 3 */
2134 /* 0x00-0x7f: VW index */
2136 /* 0x80-0x8f: Reserved1 */
2144 /* 0x93: VW Contrl 3 */
2154 /* 0x98-0x99: Reserved3 */
2163 /* 0x00-0x3f: PUT_PC Data Byte 0-63 */
2165 /* 0x40-0x7f: Reserved1 */
2167 /* 0x80-0xcf: PUT_OOB Data Byte 0-79 */
2175 /* 0x00-0x4f: Upstream Data Byte 0-79 */
2177 /* 0x50-0x7f: Reserved1 */
2179 /* 0x80-0xbf: PUT_FLASH_NP Data Byte 0-63 */
2188 * (3Axxh) SPI Slave Controller (SPISC) registers
2225 /* 0x10-0x17: Reserved1 */
2235 /* 0x1C-0x1D: Reserved2 */
2239 /* 0x1F-0x25: Reserved3 */
2252 #define IT8XXX2_SPISC_CPURXF1A BIT(3)
2260 #define IT8XXX2_SPISC_RXF1OC BIT(3)