Lines Matching +full:0 +full:x70
13 #define SOCFPGA_SYSMGR_SDMMC 0x28
15 #define SOCFPGA_SYSMGR_FPGAINTF_EN_2 0x6c
17 #define SOCFPGA_SYSMGR_EMAC_0 0x44
18 #define SOCFPGA_SYSMGR_EMAC_1 0x48
19 #define SOCFPGA_SYSMGR_EMAC_2 0x4c
20 #define SOCFPGA_SYSMGR_FPGAINTF_EN_3 0x70
22 #define SOCFPGA_SYSMGR_NOC_TIMEOUT 0xc0
23 #define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET 0xc4
24 #define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR 0xc8
25 #define SOCFPGA_SYSMGR_NOC_IDLEREQ_VAL 0xcc
26 #define SOCFPGA_SYSMGR_NOC_IDLEACK 0xd0
27 #define SOCFPGA_SYSMGR_NOC_IDLESTATUS 0xd4
29 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_0 0x200
30 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_1 0x204
31 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_2 0x208
32 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_8 0x220
33 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_9 0x224
37 #define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0)
38 #define SYSMGR_SDMMC_SMPLSEL(x) (((x) & 0x7) << 4)
40 #define IDLE_DATA_LWSOC2FPGA BIT(0)