Lines Matching +full:high +full:- +full:side

4  * SPDX-License-Identifier: Apache-2.0
21  * the system (including itself).  When the high bit becomes 1 in an
29  * the high bit of TFC is written with a 1, the value becomes ZERO,
41  * the PRID of the CPU, equal to arch_curr_cpu()->id in Zephyr) to
47  * And the other side (on cpu "dst", generally in the IDC interrupt
51  *     IDC[dst].core[src].tfc = BIT(31); // clear high bit to signal completion
59  * to signal with an interrupt via either ITC (set high "BUSY" bit) or
60  * TFC (clear high "DONE" bit).  This masking is in ADDITION to the
61  * level 2 bit for IDC in the per-core INTCTRL DSP register AND the
89  * level 2-5 interrupts).  The "mask" field shows the current masking
119 #define CAVS_L2_SHA        BIT(16)	/* SHA-256 */