20 	 (0x2 << 0))   /* "Core wake version" = 2 */
30 	 * could have come from any core, clear all of them.  in soc_mp_startup()
35 		IDC[cpu].core[i].tfc = BIT(31);  in soc_mp_startup()
38 	/* Interrupt must be enabled while running on current core */  in soc_mp_startup()
47 	/* On cAVS v2.5, MP startup works differently.  The core has  in soc_start_core()
83 	 * whether the core is being turned on again or for the first time.  in soc_start_core()
98 	 * be, so by default a core will launch successfully but then  in soc_start_core()
115 	/* Send power-up message to the other core.  Start address  in soc_start_core()
122 	IDC[curr_cpu].core[cpu_num].ietc = ietc;  in soc_start_core()
123 	IDC[curr_cpu].core[cpu_num].itc = IDC_MSG_POWER_UP;  in soc_start_core()
134 			IDC[curr].core[c].itc = BIT(31);  in send_ipi()
167 		IDC[arch_proc_id()].core[i].tfc = BIT(31);  in idc_isr()
177 	 * target core clears the busy bit.  in soc_mp_init()
181 	for (int core = 0; core < num_cpus; core++) {  in soc_mp_init()  local
182 		IDC[core].busy_int |= IDC_CORE_MASK(num_cpus);  in soc_mp_init()
183 		IDC[core].done_int &= ~IDC_CORE_MASK(num_cpus);  in soc_mp_init()
185 		/* Also unmask the IDC interrupt for every core in the  in soc_mp_init()
188 		CAVS_INTCTRL[core].l2.clear = CAVS_L2_IDC;  in soc_mp_init()
194 			IDC[i].core[j].tfc = BIT(31);  in soc_mp_init()
222 	/* Stop sending IPIs to this core */  in soc_adsp_halt_cpu()