Lines Matching full:uint32_t
25 .start = (uint32_t)__common_ram_region_start,
26 .end = (uint32_t)__common_ram_region_end,
32 .start = (uint32_t)L2_SRAM_BASE,
33 .end = (uint32_t)VECBASE_RESET_PADDR_SRAM,
38 .start = (uint32_t)VECBASE_RESET_PADDR_SRAM,
39 .end = (uint32_t)VECBASE_RESET_PADDR_SRAM + VECTOR_TBL_SIZE,
44 .start = (uint32_t)_cached_start,
45 .end = (uint32_t)_cached_end,
50 .start = (uint32_t)HP_SRAM_WIN0_BASE,
51 .end = (uint32_t)HP_SRAM_WIN0_BASE + (uint32_t)HP_SRAM_WIN0_SIZE,
56 .start = (uint32_t)HP_SRAM_WIN1_BASE,
57 .end = (uint32_t)HP_SRAM_WIN1_BASE + (uint32_t)HP_SRAM_WIN1_SIZE,
62 .start = (uint32_t)HP_SRAM_WIN2_BASE,
63 .end = (uint32_t)HP_SRAM_WIN2_BASE + (uint32_t)HP_SRAM_WIN2_SIZE,
68 .start = (uint32_t)HP_SRAM_WIN3_BASE,
69 .end = (uint32_t)HP_SRAM_WIN3_BASE + (uint32_t)HP_SRAM_WIN3_SIZE,
75 .start = (uint32_t)(IMR_BOOT_LDR_MANIFEST_BASE - IMR_BOOT_LDR_MANIFEST_SIZE),
76 .end = (uint32_t)IMR_BOOT_LDR_MANIFEST_BASE,
81 .start = (uint32_t)IMR_BOOT_LDR_MANIFEST_BASE,
82 .end = (uint32_t)(IMR_BOOT_LDR_MANIFEST_BASE + IMR_BOOT_LDR_MANIFEST_SIZE),
86 .start = (uint32_t)IMR_BOOT_LDR_BSS_BASE,
87 .end = (uint32_t)(IMR_BOOT_LDR_BSS_BASE + IMR_BOOT_LDR_BSS_SIZE),
91 .start = (uint32_t)IMR_BOOT_LDR_TEXT_ENTRY_BASE,
92 .end = (uint32_t)(IMR_BOOT_LDR_TEXT_ENTRY_BASE + IMR_BOOT_LDR_TEXT_ENTRY_SIZE),
97 .start = (uint32_t)IMR_BOOT_LDR_STACK_BASE,
98 .end = (uint32_t)(IMR_BOOT_LDR_STACK_BASE + IMR_BOOT_LDR_STACK_SIZE),
103 .start = (uint32_t)IMR_LAYOUT_ADDRESS,
105 .end = (uint32_t)(IMR_LAYOUT_ADDRESS + sizeof(struct imr_layout)),
110 .start = (uint32_t)IMR_L3_HEAP_BASE,
111 .end = (uint32_t)(IMR_L3_HEAP_BASE + IMR_L3_HEAP_SIZE),
116 .start = (uint32_t)LP_SRAM_BASE,
117 .end = (uint32_t)(LP_SRAM_BASE + LP_SRAM_SIZE),
122 .start = (uint32_t)(ADSP_L1CC_ADDR),
123 .end = (uint32_t)(ADSP_L1CC_ADDR + CONFIG_MMU_PAGE_SIZE),
129 .start = (uint32_t)0x0,
130 .end = (uint32_t)0x100000,
136 .start = (uint32_t)0x170000,
137 .end = (uint32_t)0x180000,