Lines Matching full:end
26 .end = (uint32_t)__common_ram_region_end,
33 .end = (uint32_t)VECBASE_RESET_PADDR_SRAM,
39 .end = (uint32_t)VECBASE_RESET_PADDR_SRAM + VECTOR_TBL_SIZE,
45 .end = (uint32_t)_cached_end,
51 .end = (uint32_t)HP_SRAM_WIN0_BASE + (uint32_t)HP_SRAM_WIN0_SIZE,
57 .end = (uint32_t)HP_SRAM_WIN1_BASE + (uint32_t)HP_SRAM_WIN1_SIZE,
63 .end = (uint32_t)HP_SRAM_WIN2_BASE + (uint32_t)HP_SRAM_WIN2_SIZE,
69 .end = (uint32_t)HP_SRAM_WIN3_BASE + (uint32_t)HP_SRAM_WIN3_SIZE,
76 .end = (uint32_t)IMR_BOOT_LDR_MANIFEST_BASE,
82 .end = (uint32_t)(IMR_BOOT_LDR_MANIFEST_BASE + IMR_BOOT_LDR_MANIFEST_SIZE),
87 .end = (uint32_t)(IMR_BOOT_LDR_BSS_BASE + IMR_BOOT_LDR_BSS_SIZE),
92 .end = (uint32_t)(IMR_BOOT_LDR_TEXT_ENTRY_BASE + IMR_BOOT_LDR_TEXT_ENTRY_SIZE),
98 .end = (uint32_t)(IMR_BOOT_LDR_STACK_BASE + IMR_BOOT_LDR_STACK_SIZE),
105 .end = (uint32_t)(IMR_LAYOUT_ADDRESS + sizeof(struct imr_layout)),
111 .end = (uint32_t)(IMR_L3_HEAP_BASE + IMR_L3_HEAP_SIZE),
117 .end = (uint32_t)(LP_SRAM_BASE + LP_SRAM_SIZE),
123 .end = (uint32_t)(ADSP_L1CC_ADDR + CONFIG_MMU_PAGE_SIZE),
130 .end = (uint32_t)0x100000,
137 .end = (uint32_t)0x180000,