Lines Matching full:message

17  * These registers control the DSP Communication Widget for generic sideband message transmit /
23  * Attribute register for downstream message.
31  * Destination Port ID received in message.
39  * Source Port ID received in message.
47  * Opcode received in message.
55  * Byte enables received in message.
68  * Address register (lower 32 bits) for downstream message.
72  * LSB 32 address bits received in message. Bits 32:16 of the LSB address only
80  * Address register (upper 32 bits) for downstream message.
88  * MSB 16 address bits received in message. Valid only when ADDRLEN bit is set to 1.
102  * Address length indication received in message.
111  * Extended header (SAI / RS) register for downstream message.
119  * SAI received in message. Valid if EHP bit set to 1.
127  * Root space received in message. Valid if EHP bit set to 1.
141  * Extended header present indication received in message. When set to 1 indicates
149  * Receive data register for downstream message.
153  * Data received in message.
160  * Control & status register for downstream message.
169  * 01: Posted message
170  * 10: Non-posted message
171  * 11: Completion message.
185  * Interrupt GENMASK register for message received interrupt. When set to 1 interrupt
191  * Message Received
194  * Message received interrupt status register. Set by HW when message is received,
237  * Completion SAI received for upstream non-posted message.
251  * Completion status received for upstream non-posted message
267  * Completion EH present indication received for upstream non-posted message.
299  * Status register for upstream message.
314  * Message Sent
317  * Upstream message sent interrupt status. Set by HW when upstream message has been
331  * Command register for upstream message.
353  * For posted message this register bit value will be ignored and hardcoded to 0 in
354  * the actual message as reads cannot be posted.
359  * Message Type
371  * Interrupt enable register for message sent interrupt. When cleared to 0 interrupt
385  * Address register (lower 32 bits) for upstream message.
389  * LSB 32 address bits for message to be sent.  Bits 32:16 of the LSB address only
397  * Address register (upper 32 bits) for upstream message.
405  * MSB 16 address bits for message to be sent. Valid only when ADDRLEN bit is set
420  * Address length indication for message to be sent.
423  * For simple message / message with data, this field will carry the MISC[3] of the
424  * IOSF 1.2 message format.
431  * Transmit data register for upstream message.
435  * Data for message to be sent.
442  * Attribute register for upstream message.
450  * Destination ID for message to be sent.
458  * Opcode for message to be sent.
466  * Byte enables for message to be sent.
474  * BAR for register access to be sent. For simple message / message with data, this
475  * field will carry the MISC[2:0] of the IOSF 1.2 message format. Note: MSB of this
476  * register field is not used given the IOSF Sideband message BAR field is ONLY 3
477  * bits wide; and MISC[3] of the IOSF 1.2 message format is supplied by
493  * Extended header (SAI / RS) register for upstream message.
501  * SAI for message to be sent, if EHP bit set to 1. Reset value is hardcoded to
516  * Root space for message to be sent, if EHP bit set to 1.
530  * Extended header present indication for message to be sent. When set to 1
556  * Completion status to be sent for downstream non-posted message.
573  * indicate downstream message received is consumed. This internally causes an IOSF
575  * original message is posted then upstream completion is not generated by HW. This
590  * Completion SAI to be sent for downstream non-posted message. Reset value is
682  * Receive data (second DW) register for downstream message.
686  * Data received in message. Second DW, if valid.
695  * model in ACE IP to support any boot prep message handling by FW.
705  * NOTE: If a BOOTPREP message is received, DSP FW is interrupted unconditionally,
719  * Boot prep message control register.
721  * model in ACE IP to support any boot prep message handling by FW.
729  * This bit is set by SBEP HW upon the reception of BOOTPREP message. DSP FW is
731  * BOOTPREPACK message on the upstream path of SBEP HW. SBEP HW will clear this bit,
765  * @brief Configure attributes of upstream message
767  * @param dest Destination Port ID for message to be sent.
769  * @param opcode Opcode for message to be sent.
770  * @param be Byte enables for message to be sent.
783  * @brief Set 16bit address for upstream message.
785  * @param address Address for message to be sent.
794  * @brief Set transmit data for upstream message.
796  * @param data Data for message to be sent.
804  * @brief Interrupt enable / disable for message sent interrupt.
822  * @brief Write posted message.
837  * @brief Clear message send interrupt status
848  * @brief Wait for message to be send.
858  * @brief Write a sideband message.