Lines Matching full:fw
195 * and cleared by HW when FW writes to upstream completion control register
292 * cleared by FW when writing 1 to it.
318 * sent out, and cleared by FW when writing 1 to it.
339 * DSP FW writes a 1 to this bit to cause an IOSF SB Transaction. The type of
341 * read as 0 but FW can write it to 1 to start the upstream transaction. In that way
572 * Completion for downstream request handling. DSP FW writes a 1 to this bit to
668 * Implementation Note: This FW managed TCG bit is not used as HW has been improved
695 * model in ACE IP to support any boot prep message handling by FW.
703 * This bit is set by DSP FW to enable SBEP HW to accept downstream cycles from
705 * NOTE: If a BOOTPREP message is received, DSP FW is interrupted unconditionally,
721 * model in ACE IP to support any boot prep message handling by FW.
729 * This bit is set by SBEP HW upon the reception of BOOTPREP message. DSP FW is