Lines Matching refs:t0
41 la t0, _isr_wrapper
43 add t0, zero, zero
45 addi t0, t0, 0x03 /* Enable CLIC vectored mode by setting LSB */
46 csrw mtvec, t0
60 la t0, _irq_vector_table
61 csrw 0x307, t0 /* mtvt */
77 la t0, _irq_vector_table /* Load address of interrupt vector table */
78 addi t0, t0, 0x01 /* Enable vectored mode by setting LSB */
79 csrw mtvec, t0
87 la t0, _isr_wrapper
88 addi t0, t0, 0x03 /* Set mode bits to 3, signifying CLIC. Everything else is reserved. */
89 csrw mtvec, t0
99 la t0, _isr_wrapper
100 csrw mtvec, t0