Lines Matching +full:t0 +full:- +full:out
2 * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
5 * SPDX-License-Identifier: Apache-2.0
41 la t0, _isr_wrapper
43 add t0, zero, zero
45 addi t0, t0, 0x03 /* Enable CLIC vectored mode by setting LSB */
46 csrw mtvec, t0
60 la t0, _irq_vector_table
61 csrw 0x307, t0 /* mtvt */
68 * Set mtvec (Machine Trap-Vector Base-Address Register)
71 * is used (LSB = 0x1). CPU will mask the LSB out of
74 * NOTE: _irq_vector_table is 256-byte aligned. Incorrect alignment
77 la t0, _irq_vector_table /* Load address of interrupt vector table */
78 addi t0, t0, 0x01 /* Enable vectored mode by setting LSB */
79 csrw mtvec, t0
87 la t0, _isr_wrapper
88 addi t0, t0, 0x03 /* Set mode bits to 3, signifying CLIC. Everything else is reserved. */
89 csrw mtvec, t0
96 * Set mtvec (Machine Trap-Vector Base-Address Register)
99 la t0, _isr_wrapper
100 csrw mtvec, t0