Lines Matching refs:bit
38 GCLK->GENCTRL[0].bit.SRC = GCLK_GENCTRL_SRC_OSCULP32K_Val; in gclk_reset()
39 OSCCTRL->OSC16MCTRL.bit.ENABLE = 0; in gclk_reset()
63 while (!OSC32KCTRL->STATUS.bit.OSC32KRDY) { in osc32k_init()
84 while (!OSC32KCTRL->STATUS.bit.XOSC32KRDY) { in xosc32k_init()
101 while (!OSCCTRL->STATUS.bit.OSC16MRDY) { in osc16m_init()
185 while (!OSCCTRL->STATUS.bit.DFLLRDY) { in dfll48m_init()
187 OSCCTRL->DFLLCTRL.bit.ENABLE = 1; in dfll48m_init()
191 while (!OSCCTRL->STATUS.bit.DFLLLCKC || !OSCCTRL->STATUS.bit.DFLLLCKF) { in dfll48m_init()
199 NVMCTRL->CTRLB.bit.RWS = 2; in flash_waitstates_init()
204 PM->PLCFG.bit.PLDIS = 0; in pm_init()
205 PM->PLCFG.bit.PLSEL = 2; in pm_init()
211 GCLK->GENCTRL[0].bit.SRC = GCLK_GENCTRL_SRC_DFLL48M_Val; in gclk_main_configure()