5  * SPDX-License-Identifier: Apache-2.0
26 	OSC32KCTRL->XOSC32K.reg = OSC32KCTRL_XOSC32K_ENABLE  in osc32k_init()
34 	while (!OSC32KCTRL->STATUS.bit.XOSC32KRDY) {  in osc32k_init()
37 	GCLK->GENCTRL[1].reg = GCLK_GENCTRL_SRC(GCLK_SOURCE_XOSC32K)  in osc32k_init()
44 	GCLK->GENCTRL[1].reg = GCLK_GENCTRL_SRC(GCLK_SOURCE_OSCULP32K)  in osc32k_init()
53 	/* We source the DPLL from 32kHz GCLK1 */  in dpll_init()
56 	/* disable the DPLL before changing the configuration */  in dpll_init()
57 	OSCCTRL->Dpll[n].DPLLCTRLA.bit.ENABLE = 0;  in dpll_init()
58 	while (OSCCTRL->Dpll[n].DPLLSYNCBUSY.reg) {  in dpll_init()
61 	/* set DPLL clock source to 32kHz GCLK1 */  in dpll_init()
62 	GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0 + n].reg = GCLK_PCHCTRL_GEN(1) | GCLK_PCHCTRL_CHEN;  in dpll_init()
63 	while (!(GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0 + n].reg & GCLK_PCHCTRL_CHEN)) {  in dpll_init()
66 	OSCCTRL->Dpll[n].DPLLRATIO.reg  = OSCCTRL_DPLLRATIO_LDRFRAC(LDR & 0x1F)  in dpll_init()
67 					| OSCCTRL_DPLLRATIO_LDR((LDR >> 5) - 1);  in dpll_init()
70 	OSCCTRL->Dpll[n].DPLLCTRLB.reg	= OSCCTRL_DPLLCTRLB_REFCLK_GCLK  in dpll_init()
74 	OSCCTRL->Dpll[n].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE;  in dpll_init()
76 	while (OSCCTRL->Dpll[n].DPLLSYNCBUSY.reg) {  in dpll_init()
78 	while (!(OSCCTRL->Dpll[n].DPLLSTATUS.bit.CLKRDY &&  in dpll_init()
79 		 OSCCTRL->Dpll[n].DPLLSTATUS.bit.LOCK)) {  in dpll_init()
92 	OSCCTRL->DFLLCTRLB.reg = reg;  in dfll_init()
93 	OSCCTRL->DFLLCTRLA.reg = OSCCTRL_DFLLCTRLA_ENABLE;  in dfll_init()
95 	while (!OSCCTRL->STATUS.bit.DFLLRDY) {  in dfll_init()
101 	GCLK->CTRLA.bit.SWRST = 1;  in gclk_reset()
102 	while (GCLK->SYNCBUSY.bit.SWRST) {  in gclk_reset()
108 	GCLK->GENCTRL[gclk].reg = GCLK_GENCTRL_SRC(src)  in gclk_connect()
128 	 * It is not clear if regular Cortex-M instructions can be used to  in soc_reset_hook()
132 	CMCC->CTRL.bit.CEN = 0;  in soc_reset_hook()
139 	/* use DPLL for main clock */  in soc_reset_hook()