Lines Matching +full:main +full:- +full:mode

3  * Copyright (c) 2019-2023 Gerson Fernando Budke <nandojve@gmail.com>
4  * SPDX-License-Identifier: Apache-2.0
10  * This file provides routines to initialize and support board-level hardware
29  * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot.
34 	/* Switch the main clock to the internal OSC with 12MHz */  in clock_init()
37 	/* Switch MCK (Master Clock) to the main clock */  in clock_init()
40 	EFC->EEFC_FMR = EEFC_FMR_FWS(0) | EEFC_FMR_CLOE;  in clock_init()
51 		 * Setup main external crystal oscillator.  in clock_init()
68 	EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE;  in clock_init()
75 	 * PLL clock = Main * (MULA + 1) / DIVA  in clock_init()
78 	 * With main crystal running at 12 MHz,  in clock_init()
109 		 * Instruct CPU to enter Wait mode instead of Sleep mode to  in soc_reset_hook()
119 	 * sys_cache*-functions can enable them, if requested by the  in soc_reset_hook()
144 	if (CHIPID->CHIPID_CIDR != CHIP_CIDR) {  in soc_early_init_hook()
146 			(uint32_t)CHIPID->CHIPID_CIDR, (uint32_t)CHIP_CIDR);  in soc_early_init_hook()