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3 * Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
4 * SPDX-License-Identifier: Apache-2.0
10 * This file provides routines to initialize and support board-level hardware
31 * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot.
36 /* Switch the main clock to the internal OSC with 12MHz */ in clock_init()
39 /* Switch MCK (Master Clock) to the main clock */ in clock_init()
42 EFC->EEFC_FMR = EEFC_FMR_FWS(0) | EEFC_FMR_CLOE; in clock_init()
53 * Setup main external crystal oscillator. in clock_init()
70 EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE; in clock_init()
77 * PLL clock = Main * (MULA + 1) / DIVA in clock_init()
80 * With main crystal running at 12 MHz, in clock_init()
112 * Instruct CPU to enter Wait mode instead of Sleep mode to in soc_reset_hook()
122 * sys_cache*-functions can enable them, if requested by the in soc_reset_hook()
147 if (CHIPID->CHIPID_CIDR != CHIP_CIDR) { in soc_early_init_hook()
149 (uint32_t)CHIPID->CHIPID_CIDR, (uint32_t)CHIP_CIDR); in soc_early_init_hook()