Lines Matching full:peripheral
28 /* Offset: 0x020 (r/w)AHB peripheral access control set */
30 /* Offset: 0x024 (r/w)AHB peripheral access control clear */
33 /* Offset: 0x030 (r/w)APB peripheral access control set */
35 /* Offset: 0x034 (r/w)APB peripheral access control clear */
51 /* Offset: 0x080 (r/w) AHB peripheral clock set in active state */
53 /* Offset: 0x084 (r/w) AHB peripheral clock clear in active state */
55 /* Offset: 0x088 (r/w) AHB peripheral clock set in sleep state */
57 /* Offset: 0x08c (r/w) AHB peripheral clock clear in sleep state */
59 /* Offset: 0x090 (r/w) AHB peripheral clock set in deep sleep state */
61 /* Offset: 0x094 (r/w) AHB peripheral clock clear in deep sleep state */
64 /* Offset: 0x0a0 (r/w) APB peripheral clock set in active state */
66 /* Offset: 0x0a4 (r/w) APB peripheral clock clear in active state */
68 /* Offset: 0x0a8 (r/w) APB peripheral clock set in sleep state */
70 /* Offset: 0x0ac (r/w) APB peripheral clock clear in sleep state */
72 /* Offset: 0x0b0 (r/w) APB peripheral clock set in deep sleep state */
74 /* Offset: 0x0b4 (r/w) APB peripheral clock clear in deep sleep state */
77 /* Offset: 0x0c0 (r/w) AHB peripheral reset select set */
79 /* Offset: 0x0c4 (r/w) AHB peripheral reset select clear */
81 /* Offset: 0x0c8 (r/w) APB peripheral reset select set */
83 /* Offset: 0x0cc (r/w) APB peripheral reset select clear */