Lines Matching +full:- +full:w
4 * SPDX-License-Identifier: Apache-2.0
17 /* Offset: 0x000 (r/w) remap control register */
19 /* Offset: 0x004 (r/w) pmu control register */
21 /* Offset: 0x008 (r/w) reset option register */
23 /* Offset: 0x00c (r/w) emi control register */
25 /* Offset: 0x010 (r/w) reset information register */
28 /* Offset: 0x020 (r/w)AHB peripheral access control set */
30 /* Offset: 0x024 (r/w)AHB peripheral access control clear */
33 /* Offset: 0x030 (r/w)APB peripheral access control set */
35 /* Offset: 0x034 (r/w)APB peripheral access control clear */
38 /* Offset: 0x040 (r/w) main clock control register */
40 /* Offset: 0x044 (r/w) auxiliary / rtc control register */
42 /* Offset: 0x048 (r/w) pll control register */
44 /* Offset: 0x04c (r/w) pll status register */
46 /* Offset: 0x050 (r/w) sleep control register */
48 /* Offset: 0x054 (r/w) flash auxiliary settings control register */
51 /* Offset: 0x080 (r/w) AHB peripheral clock set in active state */
53 /* Offset: 0x084 (r/w) AHB peripheral clock clear in active state */
55 /* Offset: 0x088 (r/w) AHB peripheral clock set in sleep state */
57 /* Offset: 0x08c (r/w) AHB peripheral clock clear in sleep state */
59 /* Offset: 0x090 (r/w) AHB peripheral clock set in deep sleep state */
61 /* Offset: 0x094 (r/w) AHB peripheral clock clear in deep sleep state */
64 /* Offset: 0x0a0 (r/w) APB peripheral clock set in active state */
66 /* Offset: 0x0a4 (r/w) APB peripheral clock clear in active state */
68 /* Offset: 0x0a8 (r/w) APB peripheral clock set in sleep state */
70 /* Offset: 0x0ac (r/w) APB peripheral clock clear in sleep state */
72 /* Offset: 0x0b0 (r/w) APB peripheral clock set in deep sleep state */
74 /* Offset: 0x0b4 (r/w) APB peripheral clock clear in deep sleep state */
77 /* Offset: 0x0c0 (r/w) AHB peripheral reset select set */
79 /* Offset: 0x0c4 (r/w) AHB peripheral reset select clear */
81 /* Offset: 0x0c8 (r/w) APB peripheral reset select set */
83 /* Offset: 0x0cc (r/w) APB peripheral reset select clear */
85 /* Offset: 0x0d0 (r/w) AHB power down sleep wakeup source set */
87 /* Offset: 0x0d4 (r/w) AHB power down sleep wakeup source clear */
89 /* Offset: 0x0d8 (r/w) APB power down sleep wakeup source set */
91 /* Offset: 0x0dc (r/w) APB power down sleep wakeup source clear */
93 /* Offset: 0x0e0 ( /w) rtc reset */
95 /* Offset: 0x0e4 (r/w) event interface control register */
98 /* Offset: 0x0f0 (r/w) sram power control override */
100 /* Offset: 0x0f4 (r/w) embedded flash power control override */
105 /* Offset: 0x100 (r/w) io pad settings */
107 /* Offset: 0x104 (r/w) io pad settings */
109 /* Offset: 0x108 (r/w) testmode boot bypass */